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7622965 |
Dual-edge shaping latch/synchronizer for re-aligning edges
Integrated circuit and process for aligning a first signal with a second signal. The integrated circuit includes a single latch, a switch control circuit coupled to an input of the single latch to...
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7602877 |
Frequency divider and method for controlling the same
A frequency divider in accordance with the present invention includes a plurality of latch circuits connected together in series to which a clock signal and an inversion clock signal are input, an...
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7602386 |
Reference clock signal generation circuit, power supply circuit, driver circuit, and electro-optical device
A reference clock signal generation circuit for generating a reference clock signal for a charge-pump operation which raises or lowers a voltage includes a clock signal generation circuit which...
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7602221 |
Dynamic frequency divider
A dynamic frequency divider is proposed in which a double mixer is used for the dynamic frequency division. In one example the division is by N, where N≧2 and a positive integer. The dynamic...
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7600167 |
Flip-flop, shift register, and scan test circuit
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
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7600142 |
Integrated circuit conserving power during transitions between normal and power-saving modes
An integrated circuit includes a volatile memory, a central processing unit that normally operates on a first clock, and an input-output circuit that transfers data in synchronization with a second...
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7595668 |
High speed dynamic frequency divider
The frequency divider includes the buffer 30 , the function selector 31 and the inverter 32 . The output of the function selector 31 is input to the buffer 30 . The output of the buffer 30 ...
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7583112 |
Frequency-division circuit
A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA( 1 ), . . . , SA(N); SB( 1 ), . . . ,...
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7573970 |
Prescaler and buffer
A prescaler that operates in a broad band. The prescaler includes a buffer and a counter. The buffer includes a first amplification circuit, which has three inverter circuits of different drive...
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7573305 |
High speed divider circuit
A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with...
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7567109 |
Integrated circuit devices generating a plurality of drowsy clock signals having different phases
An integrated circuit device which internally generates a plurality of drowsy clock signals having different phases is provided. The integrated circuit device includes a phase synchronizer...
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7564276 |
Low-power modulus divider stage
A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a...
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7560962 |
Generating an output signal with a frequency that is a non-integer fraction of an input signal
Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one...
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7557664 |
Injection-locked frequency divider
An injection-locked frequency divider (ILFD) can go beyond simple frequency division by an even number. In one embodiment, another differential pair of transistors is added to convert the injection...
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7557621 |
Divider
A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The...
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7551009 |
High-speed divider with reduced power consumption
A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and...
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7538590 |
Methods and apparatus for dividing a clock signal
There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is...
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7535981 |
Clock generation circuit and method thereof
The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL 1 and the frequency fref/(A+1) of a divided clock...
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7532077 |
Edge alignment for frequency synthesizers
A frequency synthesizer ( 50, 70 ) including an edge-detection circuit ( 51, 60 ) for disabling elements of the frequency synthesizer ( 50, 70 ) prior to start-up. The edge-detection circuit...
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7532049 |
Reduced-noise frequency divider system
Embodiments of a reduced noise reduction system (“RNFDS”) include a frequency divider and a resampler in signal communication with the frequency divider. The frequency divider receives an input...
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7521972 |
Fifty percent duty cycle clock divider circuit and method
In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and...
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7518418 |
Ratio granularity clock divider circuit and method
In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the...
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7518417 |
Wireless transceiver components with improved IQ matching
A frequency divider comprises a first differential input pair, a second differential input pair, a first capacitive element having first and second ends, a second capacitive element having first...
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7514977 |
Clock signal generating circuit
A clock signal generating circuit is provided. The clock signal generating circuit includes a clock signal generator for generating a first clock signal having a predetermined frequency; a...
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7514970 |
Decimal frequency synthesizer
A frequency synthesizer and method for synthesizing decimal frequencies. The synthesizer includes a seed generator, a clock synthesizer and an output synthesizer. The clock synthesizer includes a...
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7511581 |
Wide-band multimode frequency synthesizer and variable frequency divider
A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a...
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7511542 |
Frequency dividing circuit
A frequency dividing circuit includes: a D-type flip flop that outputs frequency-divided signal synchronized with input clock and reverse phase signal corresponding to the frequency-divided signal;...
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7508273 |
Quadrature clock divider
A divide-by-n process is effected via a scale-by-four/n process followed by a divide-by-four process. A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection...
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7505548 |
Circuits and methods for programmable integer clock division with 50% duty cycle
Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of...
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7504869 |
Frequency dividing circuit, power supply circuit and display device
A level shifter and a charge pump circuit are added, among cascade-connected unit frequency dividing circuits forming a frequency dividing circuit, to the unit frequency dividing circuit in the...
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7492852 |
Fractional frequency divider
A divide-by-N/(N+0.5) frequency divider is disclosed. Two pairs of flip-flops are respectively triggered by an input clock and an inverted input clock, and a frequency-dividing selector is used to...
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7486145 |
Circuits and methods for implementing sub-integer-N frequency dividers using phase rotators
Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with...
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7474134 |
Radiation hardened programmable phase frequency divider
The present invention provides a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three...
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7471123 |
Fractional-N baseband frequency synthesizer in bluetooth applications
A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock...
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7466786 |
Rational number frequency multiplier circuit and method for generated rational number frequency
A rational number frequency multiplier circuit and a method for generating rational number multiple frequency are disclosed. The circuit receives a plurality of input signals having the same...
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7459948 |
Phase adjustment for a divider circuit
A divider circuit receives an input signal and at least one phase adjustment control signal and supplies a phase adjustable output signal. The divider circuit includes a state machine providing N...
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7454301 |
Method and apparatus for predicting system noise
A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by...
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7453293 |
High frequency divider state correction circuit
The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to...
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7444534 |
Method and apparatus for dividing a digital signal by X.5 in an information handling system
An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock...
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7427883 |
High bandwidth phase locked pool (PLL)
A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a...
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7425850 |
Quadrature divider
The quadrature divider comprises a plurality of flip-flops, including at least a first flip flop and an endmost flip-flop, interoperably coupled in series to produce a predetermined dividing ratio,...
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7424087 |
Clock divider
A clock divider includes a first state storage unit, a second state storage unit a first control signal generating unit a state update unit and an output unit. The first state storage unit receives...
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7411432 |
Integrated circuits and complementary CMOS circuits for frequency dividers
An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational...
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7405601 |
High-speed divider with pulse-width control
In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first...
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7403048 |
Divider circuits and methods using in-phase and quadrature signals
Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider...
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7372310 |
Digital frequency-multiplying DLLs
Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and...
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7368958 |
Methods and systems for locally generating non-integral divided clocks with centralized state machines
A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a...
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7358782 |
Frequency divider and associated methods
The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port...
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7355460 |
Method for locally generating non-integral divided clocks with centralized state machines
A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going...
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7342425 |
Method and apparatus for a symmetrical odd-number clock divider
A method and apparatus for dividing the frequency of an input clock signal by an odd integer is disclosed. The output of two asymmetrical clock dividers may be combined to produce a divided clock...
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