Patents in Class 326/98

Matches 1 - 50 out of 700

Match	Document	Document Title
1	7592840	Domino circuit with disable feature Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.
2	7573300	Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic...
3	7570080	Set dominant latch with soft error resiliency A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the...
4	7567096	Circuit device and method of controlling a voltage swing In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device...
5	7564266	Logic state catching circuits A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state...
6	7557616	Limited switch dynamic logic cell based register A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front...
7	7545177	Method and apparatus for leakage current reduction Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic...
8	7541841	Semiconductor integrated circuit In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S 0 , a first node N 1 is L and a second node N 2...
9	7539467	Low leakage IC input structures including slaved standby current shut-off and increased gain for tighter hysteresis Leakage current at the inputs of an integrated circuit can be reduced by providing a master/slave arrangement wherein a plurality of slave inputs are controlled by an enable input acting as a...
10	7532036	Semiconductor device having a pseudo power supply wiring A semiconductor device includes main power supply wirings VDD and VSS, an pseudo power supply wiring VDT, inverters connected between the pseudo power supply wiring VDT and the main power supply...
11	7498845	Power supply switching at circuit block level to reduce integrated circuit input leakage currents Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one...
12	7492192	Logic processing apparatus, semiconductor device and logic circuit A logic processing circuit including a plurality of flip-flop including a front stage flip-flop and a rear stage flip-flop, a logic gate circuit network adapted to process data stored in the front...
13	7489161	Method for extending lifetime reliability of digital logic devices through removal of aging mechanisms A method for extending lifetime reliability of CMOS circuitry includes coupling a first switching device between a logic high supply rail/logic low supply rail, and coupling a virtual supply rail...
14	7479807	Leakage dependent online process variation tolerant technique for internal static storage node A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage...
15	7479806	Semiconductor integrated circuit device The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a...
16	7471114	Design structure for a current control mechanism for power networks and dynamic logic keeper circuits A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding...
17	7463067	Switch block for FPGA architectures A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.
18	7454589	Data buffer circuit, interface circuit and control method therefor There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
19	7443205	Relatively low standby power Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the...
20	7429880	Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) The present invention implements structures and method for non-delayed clock dynamic logic circuit configurations with output and/or complementary output with reduced glitch and/or mitigating...
21	7429879	Clock receiver circuit device, in particular for semi-conductor components A semi-conductor component with a receiver, in particular a clock receiver circuit device, as well as a receiver, in particular a clock receiver circuit device is disclosed. The clock receiver...
22	7411432	Integrated circuits and complementary CMOS circuits for frequency dividers An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational...
23	7411425	Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit A method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock...
24	7411423	Logic activation circuit Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for...
25	7405606	D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and...
26	7403042	Flip-flop, integrated circuit, and flip-flop resetting method A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a...
27	7400175	Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a...
28	7391233	Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the...
29	7389478	System and method for designing a low leakage monotonic CMOS logic circuit A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic...
30	7388400	Semiconductor integrated circuits with power reduction mechanism A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power...
31	7382161	Accelerated P-channel dynamic register A non-inverting dynamic register includes a domino stage, a mux, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal,...
32	7382157	Interconnect driver circuits for dynamic logic Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or...
33	7372305	Scannable dynamic logic latch circuit A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a...
34	7365575	Gated clock logic circuit A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated...
35	7362140	Low swing current mode logic family The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a...
36	7358775	Inverting dynamic register with data-dependent hold time reduction mechanism Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function...
37	7358768	XOR-based conditional keeper and an architecture implementing its application to match lines The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock...
38	7355454	Energy recovery boost logic A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected...
39	7345519	Flip-flop circuit A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that...
40	7342423	Circuit and method for calculating a logical combination of two input operands A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and...
41	7342421	CMOS circuit arrangement In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect...
42	7339403	Clock error detection circuits, methods, and systems Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are...
43	7336105	Dual gate transistor keeper dynamic logic A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The...
44	7323910	Circuit arrangement and method for producing a dual-rail signal Circuit arrangement for producing a dual-rail output signal having a signal processing apparatus with two switches, which are driven as a function of an input signal, a first output connected via...
45	7307457	Apparatus for implementing dynamic data path with interlocked keeper and restore devices A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during...
46	7304508	Method and apparatus for fast flip-flop Embodiments related to fast flip-flops are disclosed.
47	7298177	Method and mechanism to determine keeper size A method and apparatus for determining the size of a keeper transistor in a dynamic circuit is provided. A first portion of a dynamic circuit, comprising the keeper transistor, is analyzed to...
48	7292064	Minimizing timing skew among chip level outputs for registered output signals A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads...
49	7285986	High speed, low power CMOS logic gate A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low...
50	7282960	Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the...

Matches 1 - 50 out of 700

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