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8164361 Low power complementary logic latch and RF divider  
A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch...
8164359 Threshold logic element having low leakage power and high performance  
Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the...
8134387 Self-gating synchronizer  
A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data...
8125246 Method and apparatus for late timing transition detection  
Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are...
8120406 Sequential circuit with dynamic pulse width control  
A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such...
8120404 Flip-flop circuit with internal level shifter  
A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an...
8106678 Semiconductor integrated circuits with power reduction mechanism  
A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit...
8102189 Clock guided logic with reduced switching  
Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce...
8076956 Relatively low standby power  
A circuit includes a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and generates an output signal...
8067962 Semiconductor integrated circuit device  
A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which...
8030969 Semiconductor integrated circuit  
In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a...
8013628 Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same  
A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that...
7990180 Fast dynamic register  
A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of...
7990181 Clockless return to state domino logic gate  
A clockless return to state domino logic gate is disclosed responsive to multiple input nodes including at least one return to state node. A domino circuit presets a preset node to a second state....
7986166 Clock buffer circuit  
A clock buffer for a clock network that reduces leakage current and lowers power consumption. The clock buffer includes a first CMOS transistor, a second CMOS transistor, and a leakage current...
7982503 Dynamic circuit with slow mux input  
A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to...
7977977 Dynamic logic circuit with device to prevent contention between pull-up and pull-down device  
A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an...
7961009 Domino logic block having data holding function and domino logic including the domino logic block  
The domino logic of the general inventive concept receives a feedback signal and an input signal and outputs any one of the feedback signal and the input signal as an output signal in response to...
7961010 Dynamic logic circuit including dynamic standard cell library  
A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with...
7956662 Flip-flop circuit with internal level shifter  
A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an...
7940112 Semiconductor device  
To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor...
7940087 Clockless return to state domino logic gate  
A clockless return to state domino logic gate is disclosed responsive to multiple return to state input nodes. A domino circuit has a preset state in which it presets a preset node to a second...
7936185 Clockless return to state domino logic gate  
A clockless return to state domino logic gate including a domino circuit and an input circuit. The domino circuit asserts s preset node and an enable node to a first logic state and asserts an...
7932762 Latch and DFF design with improved soft error rate and a method of operating a DFF  
A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a...
7928769 Logic circuits with current control mechanisms  
Some embodiments regard a circuit comprising a current source network configured to generate a first current; a leakage circuit having a leakage current in at least two leakage conditions; the...
7915925 Scannable D flip-flop  
The present invention relates to scannable D flip-flops, which are improved to solve the problem of the conventional designs and provides a small and fast scannable D flip-flop without compensating...
7902878 Clock gating system and method  
A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an...
7898297 Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits  
Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A...
7895458 Power control apparatus and method thereof  
A power control apparatus including an active block in which power is always maintained in an on state and an N number of power management units having a hierarchical structure where N is a natural...
7884649 Selection of optimal clock gating elements  
Techniques in which an optimal set of clock gating elements is determined for a selected circuit design. Those clock gating elements are coupled to selected flip-flops, with the effect that those...
7880506 Resolving metastability  
A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least...
7880504 Logic stages with inversion timing control  
A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits...
7876131 Dual gate transistor keeper dynamic logic  
A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The...
7872514 Latch circuit and clock signal dividing circuit  
Latch circuit and clock signal dividing circuit comprises sequentially connected latch circuits. Each latch circuit has D-type latch with latch clock input, data input and data output. A difference...
7859310 Semiconductor integrated circuit  
In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a...
7859308 Reconfigurable logic cell made up of double-gate MOSFET transistors  
Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions...
7855578 Domino logic circuit techniques for suppressing subthreshold and gate oxide leakage  
Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology...
7852121 Domino logic circuit and pipelined domino logic circuit  
A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of...
7813368 Communication system  
A communication system includes master and slave controllers, a local device connected to the slave controller, and a communication cable having a pair of wires and connected between the master and...
7808276 Chip-to-chip communication system and method  
Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The...
7804330 Adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique  
The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given...
7800407 Multiple voltage mode pre-charging and selective level shifting  
To pre-charge a node to one of first and second voltage levels in response to inputs received at the corresponding voltage level, to selectively level shift the node from the first voltage level to...
7777522 Clocked single power supply level shifter  
First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that...
7772891 Self-timed dynamic sense amplifier flop circuit apparatus and method  
Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at...
7772890 Systems and methods for dynamic logic keeper optimization  
Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that...
7764087 Low swing domino logic circuits  
Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper...
7750667 Semiconductor integrated circuit  
A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second...
7750680 Automatic extension of clock gating technique to fine-grained power gating  
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique,...
7746140 Scannable latch  
A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic...
7746117 Complementary energy path adiabatic logic  
A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type...
Matches 1 - 50 out of 756 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >