Matches 1 - 50 out of 166 1 2 3 4 >
Match Document Document Title
7627070 Method of detecting the relative positioning of two signals and corresponding device  
A device is for detecting a relative positioning of two clock signals including a fast clock signal and a slow clock signal. The fast clock frequency may be n times greater than a slow clock...
7626420 Method, apparatus, and system for synchronously resetting logic circuits  
An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting...
7617409 System for checking clock-signal correspondence  
A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving...
7613853 Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same  
An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and...
7589565 Low-power multi-output local clock buffer  
An improved circuit for reducing a capacitance load on a processor. The circuit includes a global clock circuit capable of producing a primary timing signal. The circuit further includes a local...
7583103 Configurable time borrowing flip-flops  
Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a...
7567096 Circuit device and method of controlling a voltage swing  
In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device...
7518408 Synchronizing modules in an integrated circuit  
A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK,...
7504864 Method for controlling the evaluation time of a state machine  
A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during...
7501850 Scannable limited switch dynamic logic (LSDL) circuit  
A scannable limited switch dynamic logic (LSDL) circuit including a data input and a data output, a combinational logic circuit in communication with the data input, a pre-charge circuit in...
7480846 Iterative turbo decoder with single memory  
The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder ( 14 ) and a second decoder ( 16 ), each decoder being able to calculate extrinsic output data from...
7479806 Semiconductor integrated circuit device  
The semiconductor integrated circuit device is a semiconductor integrated circuit device having a pulse generator and a latch circuit. The pulse generator has a first charge/discharge path and a...
7454589 Data buffer circuit, interface circuit and control method therefor  
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
7429879 Clock receiver circuit device, in particular for semi-conductor components  
A semi-conductor component with a receiver, in particular a clock receiver circuit device, as well as a receiver, in particular a clock receiver circuit device is disclosed. The clock receiver...
7363560 Circuit for and method of determining the location of a defect in an integrated circuit  
According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to...
7352212 Opposite-phase scheme for peak current reduction  
We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at...
7346861 Programmable logic devices with two-phase latch circuitry  
Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least...
7339403 Clock error detection circuits, methods, and systems  
Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are...
7323909 Automatic extension of clock gating technique to fine-grained power gating  
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique,...
7301373 Asymmetric precharged flip flop  
A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During...
7298171 Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices  
A layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit design of especial utility with respect to integrated circuit devices. The...
7293190 Noisy clock test method and apparatus  
A clock filter for use in filtering an external clock signal to create an internal clock signal for use by an electronic device is provided. The clock filter receives the external clock signal and...
7285985 Event-driven logic circuit  
A logic circuit comprises: an event generator for detecting a variation in data output from a signal source to generate an event which indicates the variation of the data; a plurality of...
7282960 Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock  
A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the...
7280628 Data capture for a source synchronous interface  
Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous...
7265589 Independent gate control logic circuitry  
A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an...
7259594 Electronic circuit with a chain of processing elements  
A chain of processing element ( 10 a , 10, 10 b ) with a logic circuit ( 14 ) and a storage element ( 12 ) is provided. The storage elements ( 12 ) of all except a final processing element ( 10 b )...
7245157 Dynamic phase assignment optimization using skewed static buffers in place of dynamic buffers  
A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area,...
7230985 Look-ahead decision feedback equalizing receiver  
A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a first and a second...
7213184 Testing of modules operating with different characteristics of control signals using scan based techniques  
Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different...
7212039 Dynamic logic register  
A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The...
7202704 Leakage sensing and keeper circuit for proper operation of a dynamic circuit  
A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage...
7193444 High speed data bit latch circuit  
A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s 1 , a NAND circuit having a...
7180332 Clock synchronization circuit  
A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a...
7154305 Periodic electrical signal frequency monitoring systems and methods  
Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic...
7154303 Dynamic circuit  
In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node...
7142019 System and method for reducing power-on transient current magnitude  
System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power...
7129754 Controlled load limited switch dynamic logic circuitry  
An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one...
7095252 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates  
The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some...
7088144 Conditional precharge design in staticized dynamic flip-flop with clock enable  
A method and apparatus for creating a modified dynamic flip-flop avoids the power waste created by prior art dynamic flip-flops by including a conditional pre-charge control circuit and method....
7075336 Method for distributing clock signals to flip-flop circuits  
A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint...
7042250 Synchronization of clock signals in a multi-clock domain  
A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge...
7019560 High voltage level translator  
A circuit for controlling a piezoelectric transducer includes an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp is a positive...
7005893 High-performance clock-powered logic  
High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer ( 101 ) is used to drive the...
6981167 Programmable controller with sub-phase clocking scheme  
A parallel processor with a built-in sub-phase clocking scheme is provided to execute sequentially executed programmable logic controller (PLC) programs in a parallel method. A translator program...
6967502 Dynamic circuit  
In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node...
6943586 Method and system to temporarily modify an output waveform  
Systems and methods are disclosed for controlling an associated circuit. A clock waveform that transitions between normally high and low levels over a cycle in a first operating mode is provided to...
6933757 Timing method and apparatus for integrated circuit device  
According to one embodiment, a timing circuit ( 300 ) can include a first control circuit ( 302 ), a first clocked circuit ( 304 ), a second clocked circuit ( 306 ), and a second control circuit (...
6911846 Method and apparatus for a 1 of N signal  
The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention...
6906556 High-speed domino logic with improved cascode keeper  
A high-speed domino logic with improved cascode keeper circuit uses an inverter delay element and an additional transistor to introduce a transition delay time and node isolation time to avoid the...
Matches 1 - 50 out of 166 1 2 3 4 >