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7612577 Speedpath repair in an integrated circuit  
A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also...
7602217 Level shifter circuit with pre-charge/pre-discharge  
A level shifter circuit and method of operating therefor. The level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain....
7598774 Reduced power consumption limited-switch dynamic logic (LSDL) circuit  
An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in...
7595665 Clock gated circuit  
A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an...
7592840 Domino circuit with disable feature  
Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.
7573300 Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same  
An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic...
7570080 Set dominant latch with soft error resiliency  
A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the...
7564266 Logic state catching circuits  
A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state...
7548102 Data latch with minimal setup time and launch delay  
The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The...
7545177 Method and apparatus for leakage current reduction  
Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic...
7545175 Slew rate controlled digital output buffer without resistors  
An output buffer for an IC includes a PMOS transistor having a source coupled to an operating voltage, and an NMOS transistor serially coupled between a drain of the PMOS transistor and a...
7541841 Semiconductor integrated circuit  
In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S 0 , a first node N 1 is L and a second node N 2...
7525341 Time-balanced multiplexer switching methods and apparatus  
Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit....
7498845 Power supply switching at circuit block level to reduce integrated circuit input leakage currents  
Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one...
7492192 Logic processing apparatus, semiconductor device and logic circuit  
A logic processing circuit including a plurality of flip-flop including a front stage flip-flop and a rear stage flip-flop, a logic gate circuit network adapted to process data stored in the front...
7489161 Method for extending lifetime reliability of digital logic devices through removal of aging mechanisms  
A method for extending lifetime reliability of CMOS circuitry includes coupling a first switching device between a logic high supply rail/logic low supply rail, and coupling a virtual supply rail...
7482840 Semiconductor integrated circuit  
The semiconductor integrated circuit includes: a first transistor of a first conductivity type connected between a first power supply and an output node and turned ON according to a first clock to...
7479807 Leakage dependent online process variation tolerant technique for internal static storage node  
A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage...
7474122 High-performance static programmable logic array  
A high-performance programmable logic array (PLA) includes an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is...
7471115 Error correcting logic system  
The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an...
7471114 Design structure for a current control mechanism for power networks and dynamic logic keeper circuits  
A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding...
7459940 Local clock buffer (LCB) with asymmetric inductive peaking  
A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with...
7454589 Data buffer circuit, interface circuit and control method therefor  
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
7443205 Relatively low standby power  
Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the...
7428568 Symmetric cascaded domino carry generate circuit  
A symmetric differential domino carry generate gate. In an embodiment, the load for the true inputs is equal to the load for the compliment inputs. In another embodiment, the output drive strength...
7427875 Flip-flop circuit  
Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and...
7417465 N-domino output latch  
An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock...
7411423 Logic activation circuit  
Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for...
7405606 D flip-flop  
A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and...
7403042 Flip-flop, integrated circuit, and flip-flop resetting method  
A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a...
7391233 Method and apparatus for extending lifetime reliability of digital logic devices through removal of aging mechanisms  
An apparatus for extending lifetime reliability of CMOS circuitry includes a first switching device between a logic high supply rail/logic low supply rail, and a virtual supply rail coupled to the...
7389478 System and method for designing a low leakage monotonic CMOS logic circuit  
A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic...
7388470 Comparator having small size and improved operating speed  
A comparator having a small number of logic circuits and an improved operating speed is provided, where the comparator includes m number of bit comparators, each connected between a first node and...
7372305 Scannable dynamic logic latch circuit  
A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a...
7368953 Buffer  
A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit...
7365575 Gated clock logic circuit  
A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated...
7358775 Inverting dynamic register with data-dependent hold time reduction mechanism  
Dynamic logic register including evaluation logic, delay logic, latching logic, and a keeper circuit. The evaluation logic evaluates a logic function based on data input. The logic function...
7355455 Low power consumption MIS semiconductor device  
A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an...
7352212 Opposite-phase scheme for peak current reduction  
We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at...
7346861 Programmable logic devices with two-phase latch circuitry  
Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least...
7345519 Flip-flop circuit  
A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that...
7339403 Clock error detection circuits, methods, and systems  
Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are...
7332937 Dynamic logic with adaptive keeper  
Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit....
7332932 Serial link receiver with wide input voltage range and tolerance to high power voltage supply  
A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a...
7323909 Automatic extension of clock gating technique to fine-grained power gating  
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique,...
7321243 P-domino register with accelerated non-charge path  
A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one...
7307457 Apparatus for implementing dynamic data path with interlocked keeper and restore devices  
A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during...
7304508 Method and apparatus for fast flip-flop  
Embodiments related to fast flip-flops are disclosed.
7301373 Asymmetric precharged flip flop  
A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During...
7301372 Domino logic compatible scannable flip-flop  
A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an...
Matches 1 - 50 out of 467 1 2 3 4 5 6 7 8 9 10 >