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5287536 |
Nonvolatile memory array wordline driver circuit with voltage translator circuit
A circuit for driving a wordline or group of wordlines in a floating-gate type EEPROM cell array includes a read-driver subcircuit for switching positive read voltages, a program-driver subcircuit...
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5287018 |
Dynamic PLA time circuit
A dynamic PLA timing circuit in a PLA ROM includes a PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and...
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5285116 |
Low-noise high-speed output buffer and method for controlling same
A low-noise high-speed output buffer receives digital control signals for varying the switching delay and di/dt of the buffer. For a plurality of output buffers, one buffer is used to determine the...
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5272397 |
Basic DCVS circuits with dual function load circuits
Disclosed is a basic DCVS (differential cascode voltage switch) tree construct, which can be used as a uniform basis for constructing DCVS logic circuits, register-latch circuits and circuits which...
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5268596 |
Method and apparatus for latching data around a logical data processor
A control method for a data processing circuit which controls the timing of two clocks which independently control data latch circuits connected respectively with an input side and an output side...
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5264738 |
Flip-flop circuit having transfer gate delay
The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by...
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5265064 |
Pulse generator circuit arrangement
A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining...
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5258666 |
CMOS clocked logic decoder
The present semiconductor logic circuit includes a first-stage logic circuit section comprising of a first precharging transistor, a first grounding transistor, and a first logic element and a...
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5250852 |
Circuitry and method for latching a logic state
A method and circuitry are provided for latching a logic state. A first signal (64) indicates a logic state of an input signal (D) in response to a first transition of a clock signal (72). A second...
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5175446 |
Demultiplexer including a three-state gate
A demultiplexer includes a plurality of transistors having conduction paths connected between an input terminal and output nodes. The control electrode of every transistor is connected to one line...
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5168463 |
Shift register apparatus for storing data therein
An apparatus for storing digital data includes a clock pulse source and plural serial shift register stages storing data bits. Digital data signals, each having plural databits, are coupled to and...
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5153455 |
Transition-based wired "OR" for VLSI systems
A transition-based wired "OR" bus circuit for use on a VLSI system including a common bus line and a plurality of I.C. chips connected to the bus line permits interchip communication among the...
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5146115 |
Domino-logic decoder
A domino-logic decoder which decodes an input in an amount of time substantially independent on the bit size of the input. An address is input to a stack of at least two individually gated...
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5146110 |
Semiconductor memory with substrate voltage generating circuit for removing unwanted substrate current during precharge cycle memory mode of operation
A semiconductor memory device having a substrate voltage production circuit comprises a time delay circuit. The time delay circuit of the present invention has a simple construction and is provided...
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5140180 |
High speed CMOS flip-flop employing clocked tristate inverters
A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel...
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5124578 |
Receiver designed with large output drive and having unique input protection circuit
A high voltage level input protection, high capacitance output IC clock receiver uses a ratioed CMOS buffer for the output drive and the receiver includes a low resistance input circuit having a...
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5122681 |
Synchronous BiCMOS logic gate
A synchronous BiCMOS logic circuit which operates between two voltage supplies and has at least one input terminal, an intermediate node and an output terminal is disclosed. The logic circuit is...
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5117130 |
Integrated circuits which compensate for local conditions
Apparatus for compensating for the effect of a local condition on an active element in a portion of an integrated circuit. The apparatus includes a detecting element in the portion of the...
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5115150 |
Low power CMOS bus receiver with small setup time
A complementary metal oxide semiconductor (CMOS) inverter circuit wherein the complementary PFET is replaced by a small CMOS inverter and an NFET having a size substantially the same as that of the...
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5093588 |
Bus circuit of precharge type for semiconductor integrated circuit
A bus circuit of a precharging type has an hierarchical structure comprising a higher rank bus and a plurality of lower rank buses connected in parallel thereto. A register block is connected to...
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5075576 |
Field-programmable logic device with programmable foldback to control number of logic levels
A monolithic integrated circuit contains a field-programmable logic architecture centered on a single array of programmable gates that perform either logical NAND or logical NOR operations....
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4992678 |
High speed computer data transfer system
A high speed computer data transfer system includes a clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus...
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4959646 |
Dynamic PLA timing circuit
A dynamic PLA timing circuit in a PLA ROM includes a first PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address...
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4933571 |
Synchronizing flip-flop circuit configuration
A synchronizing flip-flop circuit configuration for synchronizing data includes an input and an output of the synchronizing flip-flop circuit configuration. A first transfer gate, connected to the...
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4922122 |
Circuit for the detection of address transitions
A circuit for the detection of address transistions in an integrated circuit comprises a logic signal input terminal, a D flip-flop for memorizing the state of the input signal, and a comparator...
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4902911 |
Semiconductor integrated circuit having a built-in power voltage generator
A semiconductor integrated circuit having a voltage generator circuit for generating an internal power voltage lower than an externally supplied power voltage, a control circuit for generating at...
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4896057 |
High-speed dynamic domino circuit implemented with gaas mesfets
A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel...
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4740715 |
Self substrate bias generator formed in a well
The invention relates to a self substrate bias generator. A well is formed in a semiconductor substrate. The first capacitor is connected between the terminal to which the first clock signal is...
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4733405 |
Digital integrated circuit
A digital integrated circuit incorporates a plurality of multi-port flip-flop circuits which are interconnected by a plurality of gate circuits. A separate source of clock pulses is provided for...
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4656368 |
High speed master-slave flip-flop
A flip-flop including a master section having an input for receiving a data signal and a pair of outputs, one output for providing the data signal state, and one output for providing the data...
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4644185 |
Self clocking CMOS latch
A CMOS latch is coupled to a differential driver that is operated from the input data. Driver conduction is determined by the conduction in a strobe transistor responding to the signal of a strobe...
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4556806 |
Gate alterable output buffer
An electronic output buffer includes an inverter connected to an input line with several circuit devices for driving an output. The buffer further includes the programmable capability at...
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4538288 |
Shift register circuit with multiple, tapped outputs having pull-down transistors
A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the...
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4518865 |
Misoperation prevention circuit
A misoperation prevention circuit for preventing the misoperation of the integrated circuit having standby made. The misoperation prevention circuit comprises an integrator for receiving a control...
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4506165 |
Noise rejection Set-Reset Flip-Flop circuitry
Set-Reset Master-Slave Flip-Flop circuitry uses a feedback circuit connected to a circuitry output terminal and to set and reset input terminals to limit the effect of spurious signals such that...
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4503550 |
Dynamic CCD input source pulse generating circuit
A pulse generator circuit for applying a pulse signal to the input source electrode of a charge coupled device (CCD) having a "fill and spill" input operation, includes a voltage reference circuit...
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4473760 |
Fast digital sample resolution circuit
A fast digital sample resolution circuit comprising a dynamic ratioless inverter coupled to a static ratioed inverter, with positive capacitive feedback. A transistor node is precharged to one...
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4275316 |
Resettable bistable circuit
A resettable D type flip flop for integrated circuit counter circuits, which flip flop comprises master and slave flip flop stages. The slave flip flop stage includes NOR and an INVERTER circuit...
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4115796 |
Complementary-MOS integrated semiconductor device
Formation of well-regions of a conductivity type opposite to that of a substrate is achieved in such a manner to determine a first threshold voltage level. Ion implantation is effected on desirably...
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4114049 |
Counter provided with complementary field effect transistor inverters
A binary counter provided with complementary field effect transistor inverters which includes at least three complementary field effect transistor inverters, at least two of which comprise clocked...
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4107550 |
Bucket brigade circuits
The underlying concept of the invention disclosed is the use of charge partitioning for providing a precision weighted tap in a bucket brigade circuit. At the drain node of a charge conducting...
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4049974 |
Precharge arithmetic logic unit
A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes, on a single chip, an arithmetic logic unit (ALU), an instruction register, a...
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4034238 |
Field effect transistor information transfer circuit for use in storage register
An output device of a metal-insulator-semiconductor transistor integrated circuit comprises, according to the invention, a penultimate stage, an output transistor, a clock pulse terminal and a...
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4024416 |
Method for controlling frequency of electrical oscillations and frequency standard for electronic timepiece
A frequency standard for an electronic timepiece comprising a low frequency oscillator and a high frequency oscillator of which the frequency is an integral multiple of a predetermined frequency of...
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4016430 |
MIS logical circuit
In a logical circuit comprising a load and a driving MISFET, a depletion type MISFET is connected between the load and the driving MISFET and a voltage which has a smaller absolute value than the...
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4002926 |
High speed divide-by-N circuit
Disclosed is a high speed divide-by-N circuit which uses both a synchronous down-counter and a ripple down-counter to obtain the advantages of each. The advantage of a ripple counter is that count...
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3992703 |
Memory output circuit
A unique memory output integrated circuit disclosed including a memory output driver having an output terminal at which data may be read, a gated power amplifier, and a single ended multiplexer...
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3965460 |
MOS speed-up circuit
A speed-up circuit, which may be used to speed up the sensing of a bit-sense line of an MOS RAM, includes a crosscoupled latch circuit having an output suitable for coupling to an output circuit...
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3965459 |
Selectable eight or twelve digit integrated circuit calculator and conditional gate output signal modification circuit therefor
An integrated circuit calculator which can operate in either a twelve digit or an eight digit mode is provided. A conditional modification circuit modifies some of the memory addresses employed in...
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3947829 |
Logical circuit apparatus
A plurality of logical control circuits each having a storage or delay function are driven by a writing-in clock pulse φ1 and a reading-out clock pulse φ2 supplied in common thereto and receiving...
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