Matches 351 - 400 out of 468 < 1 2 3 4 5 6 7 8 9 10 >
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6005418 Low power consuming logic circuit  
Disclosed is a low power consuming logic circuit to restrain a short circuit current which flows within an inverter circuit of an inverter having a clock input connected behind a pass-transistor...
5999019 Fast CMOS logic circuit with critical voltage transition logic  
A CMOS Critical Voltage Transition Logic device which reduces propagation delays in a circuit by preconditioning the voltage outputs of each stage of the circuit to a critical voltage value which...
5986475 Apparatus and method for resetting a dynamic logic circuit  
An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a...
5982197 Dynamic circuit  
A dynamic circuit that prevents a malfunction, even when the operating temperature is high, including a pre-charging circuit connected between a power source node and a signal wiring, a plurality...
5955896 Input buffer using a differential amplifier  
In an input circuit for semiconductor devices, such as an address buffer, an arrangement is provided which obviates the timing margin from capture of an input signal to its latching and outputting,...
5936449 Dynamic CMOS register with a self-tracking clock  
A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock...
5910735 Method and apparatus for safe mode in dynamic logic using dram cell  
A dynamic logic circuit operates in a normal mode, and in a safe mode for which the circuit is less susceptible to noise than with the normal mode. The dynamic logic circuit includes a logic...
5903170 Digital logic design using negative differential resistance diodes and field-effect transistors  
A digital logic gate circuit including a logic block, clock transistor, bias transistor and a negative differential resistance (NDR) diode which acts as an active load for the circuit. The logic...
5854567 Low loss integrated circuit with reduced clock swing  
The integrated circuit with a clock system, particularly a CMOS circuit with extensive pipelining, whereby an optimally low overall dissipated power is effected in that a clock driver circuit is...
5838169 NMOS charge-sharing prevention device for dynamic logic circuits  
A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock...
5838170 PMOS charge-sharing prevention device for dynamic logic circuits  
A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock...
5821778 Using cascode transistors having low threshold voltages  
In a preferred logic circuit embodiment (164), there is a signal path and a high threshold voltage transistor (46b) having a first threshold voltage and coupled to the signal path. The logic...
5815005 Power reduction circuits and systems for dynamic logic gates  
In a preferred embodiment there is a logic circuit (230) which includes both a first (231) and second (232) phase dynamic logic circuit, where each such circuit has a one or more dynamic logic...
5815687 Apparatus and method for simulating domino logic circuits using a special machine cycle to validate pre-charge  
A domino logic simulator for a CMOS domino logic circuit seeds all logic circuits under test with an "X" state before initialization of a special simulator machine cycle devoted to validating all...
5712826 Apparatus and a method for embedding dynamic state machines in a static environment  
An apparatus and a method for embedding a dynamic state machine in a static integrated circuit environment. A static integrated circuit environment which is capable of suspending operation during a...
5661675 Positive feedback circuit for fast domino logic  
A logic circuit is described. The logic circuit generates a first signal state in response to a first set of input signals, generates a second signal state in response to a second set of input...
5650735 Low power, high performance latching interfaces for converting dynamic inputs into static outputs  
A circuit (51) for converting a pair of precharged dynamic logic signals into a static logic signal includes a first input (61) to receive one of said dynamic logic signals, a second input (67) to...
5587666 Sense amplifier slew circuitry  
A pre-charge load device to pre-charge an input on a sense amplifier is coupled between a positive voltage rail and the input to the sense amplifier and is biased by a bias network coupled between...
5572150 Low power pre-discharged ratio logic  
A circuit and method are provided for reducing the DC power consumption of clocked ratioed digital logic circuits. The circuit includes switching circuitry designed to analyze the voltage...
5532622 Multi-input transition detector with a single delay  
A transition detector circuit produces an output pulse upon detection of a transition at any one of several input nodes using a single delay path so all input transitions produce the same output...
5530659 Method and apparatus for decoding information within a processing device  
In a decoding apparatus (100), overflow conditions can be determined within the same clock cycle by determining the type of operation to be performed. For time sensitive operations, a load (102)...
5521538 Adiabatic logic  
Clocked low power logic circuitry with static inputs and outputs is adiabatically operated. A variety of logical functions is achieved without complex circuitry or unusually configured devices....
5506519 Low energy differential logic gate circuitry having substantially invariant clock signal loading  
An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two...
5502407 Low-power-dissipation CMOS circuits  
In low-power-dissipation CMOS circuitry, conventional CMOS inverters are powered by a repetitively ramped power supply. Clock signals are needed in the circuitry for controlling data flow therein....
5495188 Pulsed static CMOS circuit  
A pulsed static CMOS circuit. Improved static CMOS circuit speed is achieved without using a clock scheme like that in dynamic CMOS circuits. The disclosed circuit family is a pulsed static CMOS...
5483181 Dynamic logic circuit with reduced charge leakage  
A dynamic logic circuit with reduced charge leakage includes a dynamic complementary MOSFET logic circuit with a P-type MOSFET, a number of N-type MOSFETs and a static CMOSFET inverter circuit. In...
5479112 Logic gate with matched output rise and fall times and method of construction  
A logic gate with highly matched output rise and fall times is provided which includes at least one stacked transistor pair (24) and at least one complementary stacked transistor pair (30)...
5473270 Adiabatic dynamic precharge boost circuitry  
Power dissipation in precharge paths used in adiabatic dynamic logic circuitry is reduced by a precharge boost circuit which decreases the impedance between a clock node and an output node in such...
5471158 Pre-charge triggering to increase throughput by initiating register output at beginning of pre-charge phase  
A pre-charge triggering technique used in connection with a synchronous pipeline stage (FIG. 1b) that includes an input register (11) that feeds a function section (12) with both non-pre-charged...
5471512 Phase-locked loop configuration  
A phase-locked loop configuration includes a controllable delay device having a signal path with at least one inverter having supply lines, at least one field effect transistor having a load path,...
5450019 Precharging output driver circuit  
A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a...
5422582 Diode coupled CMOS logic design for quasi-static resistive dissipation with multi-output capability  
CMOS logic circuitry powered by the clock signals wherein the addition of strategically placed diodes enables the circuits to behave in an adiabatic-like fashion.
5416431 Integrated circuit clock driver having improved layout  
An application specific integrated circuit (ASIC) clock driver is built under the power supply second level (metal2) buses, with the p-channel and n-channel transistors lying under the V DD and V...
5392423 Universal pipeline latch for mousetrap logic circuits  
Vector logic is implemented by pipelining logic stages comprised of dynamic mousetrap logic gates. A novel pipeline latch is associated with each logic stage of the pipeline. Each pipeline latch...
5384493 Hi-speed and low-power flip-flop  
A semiconductor integrated circuit comprises a pair of complementary groups of MOS transistors disposed between first and second reference potentials and switched on and off through a pair of...
5382844 Logic circuit for asynchronous circuits with n-channel logic block and p-channel logic block inverse thereto  
A logic circuit for asynchronous circuits, in which logic circuit signals which are present at the input (in) of the logic circuit can be linked both in a first logic block (NL) and also in a...
5377158 Memory circuit having a plurality of input signals  
A multi-input memory circuit including a first input gate for selecting one of a plurality of data signals, a first inverting gate for receiving the output of the first input gate as an input, a...
5376848 Delay matching circuit  
A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The...
5355004 Semiconductor integrated circuit device having wiring for clock signal supply  
A semiconductor integrated circuit device wherein terminals other than clock signal terminals in circuit blocks are connected via a first wiring layer to a clock signal source and only the clock...
5341048 Clock invert and select circuit  
A system and method for selectively inverting a clock signal. Clock (CLK) and inverted clock (NCLK) signals are generated. A control signal (RCTL) and inverted control signal (NRCTL) operate the...
5329176 Self-timed clocking system and method for self-timed dynamic logic circuits  
A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed...
5327392 Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise  
A semiconductor integrated circuit includes a circuit block whose operation is controlled by a inverted control signal whose significant potential level is set at a ground potential, and a wiring...
5327026 Self-timed bootstrap decoder  
A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a...
5313435 Semiconductor memory device having address transition detector  
An address transition detector (ATD) of a semiconductor memory device. In particular, even if the address transition of the semiconductor memory device occurs over a long time, malfunction is...
5313120 Address buffer with ATD generation  
An address buffer (20) provides an ATD pulse in response to an address signal transitioning from one logic state to another. The address buffer (20) includes a differential amplifier (22), an...
5311073 High voltage CMOS circuit with NAND configured logic gates and a reduced number of N-MOS transistors requiring drain extension  
In a CMOS logic circuit destined to function at a relatively high supply voltage such as to require the formation of graded diffusions in the structure of N-MOS transistors, a NAND configuration is...
5309045 Configurable logic element with independently clocked outputs and node observation circuitry  
A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data...
5306962 Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing  
A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which...
5291078 Gate circuits in transition detection input buffers  
A NAND gate circuit system that provides for adjustable pulse width that comprises eight transistors arranged so that a signal can propagate through the transistors in series, the transistors...
5291076 Decoder/comparator and method of operation  
A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the...
Matches 351 - 400 out of 468 < 1 2 3 4 5 6 7 8 9 10 >