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6285217 Dynamic logic circuits with reduced evaluation time  
Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input...
6285216 High speed output enable path and method for an integrated circuit device  
A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which...
6278296 Dynamic logic circuit and integrated circuit device using the logic circuit  
In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a...
6275070 Integrated circuit having a high speed clock input buffer  
An integrated circuit (100) includes an input buffer circuit (122) having an input stage (150), a delay element (178), inverter (176), and a level shifter (156). The input stage (150) receives an...
6271684 Method and apparatus for stalling OTB domino circuits  
A circuit for stalling data in a domino pipeline. The circuit includes a logic network having multiple inputs coupled to receive multiple input data signals. The logic network generates an output...
6265897 Contention based logic gate driving a latch and driven by pulsed clock  
A pseudo-NMOS logic gate of an integrated circuit chip is enabled for a time interval that is substantially less than one-half a clock cycle of the integrated circuit. A latch responds to an output...
6265899 Single rail domino logic for four-phase clocking scheme  
A single rail domino logic circuit using a four-phase clocking scheme. A stacked PMOS pair provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement...
6259275 Logic gate having reduced power dissipation and method of operation thereof  
A circuit for, and method of, decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method. In one embodiment, wherein the logic gate has at least two...
6255854 Feedback stage for protecting a dynamic node in an integrated circuit having dynamic logic  
An integrated circuit having dynamic logic (20) is disclosed that includes a dynamic node (NODE 1). A feedback stage protects the dynamic node (NODE 1) and includes a controllable current path (26)...
6255853 Integrated circuit having dynamic logic with reduced standby leakage current  
An integrated circuit (10) is disclosed that has a dynamic logic stage (12) with reduced standby leakage current. The integrated circuit (10) includes a logic gate (20) coupled to a dynamic node...
6252417 Fault identification by voltage potential signature  
A logic gate is provided that comprises a sensing circuit coupled to a test output and to an internal node of the logic gate. The sensing circuit is adapted to sense a voltage on the internal node...
6246265 Semiconductor integrated logic circuit with sequential circuits capable of preventing subthreshold leakage current  
A semiconductor integrated logic circuit device with a sequential circuit includes a transferring section, an inverting section, a bistable circuit section, and a blocking section. The transferring...
6246266 Dynamic logic circuits using selected transistors connected to absolute voltages and additional selected transistors connected to selectively disabled voltages  
A dynamic logic circuit (16) operable in an active mode and in a power down mode, where the active mode comprises a precharge phase and an evaluate phase. The dynamic logic circuit comprises a...
6239621 Two legged reset controller for domino circuit  
A method is provided for precharging a node in an integrated circuit in which the node is precharged a first predetermined delay after the node evaluates and, thereafter, the precharge ceases after...
6239620 Method and apparatus for generating true/complement signals  
A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a...
6236241 Redundant decoder having fuse-controlled transistor  
A redundant decoder having fuse-controlled transistor comprises as follows: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an...
6232798 Self-resetting circuit timing correction  
A system and method with a self-reset circuit for synchronizing an input data path with a timing control path. The self-resetting circuit includes a normal-mode input detect circuit which detects...
6232797 Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities  
Integrated circuit devices include a data buffer that is responsive to a control signal, enabled to pass data received at a data input thereof to a data output thereof when the control signal is in...
6225826 Single ended domino compatible dual function generator circuits  
In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage...
6208170 Semiconductor integrated circuit having a sleep mode with low power and small area  
A semiconductor integrated circuit includes a power supply circuit having a global source line VCC, a local source line QVCC coupled to VCC by a source switching transistor, and a global ground...
6204696 Domino circuits with high performance and high noise immunity  
In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is...
6201425 Method and apparatus for reducing charge sharing and the bipolar effect in stacked SOI circuits  
A top clock stacked circuit is provided that substantially prevents charge sharing and that prevents any deleterious bipolar effect. The top clock stacked circuit comprises a primary pre-charge...
6191618 Contention-free, low clock load domino circuit topology  
A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output...
6184718 Dynamic logic circuit  
A dynamic logic circuit that uses substantially constant power and that has substantially constant propagation delay, independent of the number of inputs the dynamic logic circuit contains. In one...
6163172 Clock loss detector  
A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current"...
6160422 Power saving clock buffer  
A power saving clock buffer comprises a first control stage installed between a clock output and a first switch stage for controlling the state of the first switch stage. A second switch stage...
6150848 Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication  
A two-phase dynamic logic circuit for complementary GaAs HIGFET fabrication processes has a precharge transistor connected between a precharge volt source and an output node of the logic circuit....
6150846 Bus circuit  
A bus circuit of this invention has a bus line. A bus input circuit and a bus output circuit are connected to the bus line. The bus line is charged by a precharge circuit. The bus output circuit...
6133758 Selectable self-timed replacement for self-resetting circuitry  
A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the...
6107834 Charge sharing protection for domino circuits  
An embodiment of the present invention includes a switchable conductive pathway between a number of intermediate nodes in a domino stage, up to and including every intermediate node, and a voltage...
6107835 Method and apparatus for a logic circuit with constant power consumption  
The present invention comprises a method and apparatus for a logic circuit with constant power consumption. The logic circuit comprises a 1 of P first input signal that further comprises a...
6108805 Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits  
Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic...
6104667 Clock control circuit for generating an internal clock signal with one or more external clock cycles being blocked out and a synchronous flash memory device using the same  
A clock control circuit receives an external clock signal and generates an internal clock signal. Through use of internal programming and an external trigger signal, the clock control circuit...
6104212 Common domino circuit evaluation device  
A domino CMOS circuit has a number of domino gates, a common virtual ground node and a common evaluation NFET device. Each domino gate provides a PFET precharge device, an NFET device tree, an...
6097207 Robust domino circuit design for high stress conditions  
A domino circuit design for handling high stress conditions. The domino logic circuit includes a programmable mechanism for choosing whether the circuit is operating during normal operations or...
6081130 Clock controlled exclusive or circuit  
An exclusive OR circuit (10) includes an input stage (11) and a control arrangement (12,13) for controlling an exclusive OR logical evaluation. The control arrangement includes a pre-charge stage...
6081136 Dynamic NOR gates for NAND decode  
A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input...
6081135 Device and method to reduce power consumption in integrated semiconductor devices  
According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in...
6075385 Intelligent precharger for a dynamic bus  
A method and apparatus for precharging a dynamic bus on either phase of a clock signal is presented. An intelligent precharger in accordance with the invention monitors a dynamic bus and detects...
6066964 Dynamic bus  
A bi-phase, single-wire dynamic bus for allowing communication during either of a first phase or a second phase of a clock signal is presented. A data signal that is to be written onto a single bus...
6060907 Impedance control circuit  
An impedance control circuit is provided which controls the output impedance of drivers which are coupled to the impedance control circuit. Accordingly, a desired driver output impedance can...
6057711 Circuit arrangement and method for asynchronous control of logic circuits  
A circuit arrangement, system, and method provide asynchronous control of a state logic circuit to facilitate testing of the state logic circuit. The state logic circuit includes stages selectively...
6049231 Dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output  
A dynamic multiplexer circuit (20) comprising an integer number N of data providing circuits (26, 28, 30), wherein the integer number N is greater than one. Each of the plurality of data providing...
6046606 Soft error protected dynamic circuit  
A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are...
6043696 Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop  
A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the...
6040716 Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage  
A logic circuit (18) comprising a first phase domino logic circuit (20) and a second phase domino logic circuit (22). Each of the domino logic circuits comprises a precharge node (20 PN , 22 PN ),...
6037804 Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs  
A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data...
6028454 Dynamic current mode logic family  
A dynamic current mode circuit for low-voltage and high performance VLSI applications, comprising a MOS current mode logic block and dynamic circuitry for precharging the outputs of the MOS current...
6025738 Gain enhanced split drive buffer  
A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal...
6016065 Charges recycling differential logic(CRDL) circuit and storage elements and devices using the same  
A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at...
Matches 301 - 350 out of 468 < 1 2 3 4 5 6 7 8 9 10 >