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8878569 Self-recovering bus signal detector  
A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a...
8760208 Latch with a feedback circuit  
An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the...
8742792 Switching circuits, latches and methods  
Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching...
8638122 Apparatus for metastability-hardened storage circuits and associated methods  
A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of...
8559576 Adaptive synchronization circuit  
Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and...
8395417 Digital noise filter  
A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output...
8384437 Method and apparatus for gating a clock signal  
A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing...
8354870 Switching clock sources  
A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the...
8332800 Method for identifying redundant signal paths for self-gating signals  
A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a...
8289050 Switching circuits, latches and methods  
Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching...
8160859 Medium storing logic simulation program, logic simulation apparatus, and logic simulation method  
A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal...
8143930 Method and apparatus for amplifying a time difference  
Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an...
8134387 Self-gating synchronizer  
A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data...
8063682 Semiconductor circuit for performing signal processing  
A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided...
8049529 Fault triggerred automatic redundancy scrubber  
A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is...
7982502 Asynchronous circuit representation of synchronous circuit with asynchronous inputs  
A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a...
7977976 Self-gating synchronizer  
A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data...
7952391 Digital noise filter  
A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output...
7928768 Apparatus for metastability-hardened storage circuits and associated methods  
A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of...
7888971 Verification support system and method  
A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a...
7880506 Resolving metastability  
A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least...
7882473 Sequential equivalence checking for asynchronous verification  
Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to...
7825696 Even-number-stage pulse delay device  
The even-number-stage pulse delay includes a ring delay line constituted of an even number of inverter circuits connected in a ring around which main edge and a reset edge circulate together. The...
7795921 Semiconductor integrated circuit and method of reducing noise  
A semiconductor integrated circuit includes a sampling unit, a delay unit, a first operating unit and a second operating unit. The sampling unit samples an input signal supplied from an external...
7746116 Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis  
One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a...
7671633 Glitch free 2-way clock switch  
The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer...
7667489 Power-on reset circuit for a voltage regulator having multiple power supply voltages  
A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The...
7650454 Arbiter module providing low metastability failure probability  
An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving...
7626420 Method, apparatus, and system for synchronously resetting logic circuits  
An apparatus, system, and method are described for synchronously resetting logic circuits. A synchronous reset signal is coupled to at least one asynchronous reset input for synchronously resetting...
7484023 Computer system apparatus for stabilizing asynchronous interfaces  
A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic,...
7454589 Data buffer circuit, interface circuit and control method therefor  
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
7383370 Arbiter circuit and signal arbitration method  
An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can...
7359468 Apparatus for synchronizing clock and data between two domains having unknown but coherent phase  
A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling...
7340541 Method of buffering bidirectional digital I/O lines  
A system and method for buffering bidirectional digital input/output (I/O) lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional...
7337345 Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal  
The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is...
7288969 Zero clock delay metastability filtering circuit  
A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being...
7230985 Look-ahead decision feedback equalizing receiver  
A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a first and a second...
7225283 Asynchronous arbiter with bounded resolution time and predictable output state  
An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent...
7202704 Leakage sensing and keeper circuit for proper operation of a dynamic circuit  
A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage...
7180332 Clock synchronization circuit  
A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a...
7132858 Logic circuit  
A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input...
7106091 Circuit configuration and method for detecting an unwanted attack on an integrated circuit  
A circuit configuration for detecting an unwanted attack on an integrated circuit has a signal line to which a clock signal is applied and at least one line pair which is respectively used to code...
7095252 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates  
The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some...
7091742 Fast ring-out digital storage circuit  
A static storage element distorts metastable feedback signals in an unbalanced feedback loop with the resulting metastable signals eroding and being suppressed as they circulate in the loop. The...
7088144 Conditional precharge design in staticized dynamic flip-flop with clock enable  
A method and apparatus for creating a modified dynamic flip-flop avoids the power waste created by prior art dynamic flip-flops by including a conditional pre-charge control circuit and method....
7075336 Method for distributing clock signals to flip-flop circuits  
A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint...
7042250 Synchronization of clock signals in a multi-clock domain  
A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge...
6995585 System and method for implementing self-timed decoded data paths in integrated circuits  
A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding...
6960941 Latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits  
A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and...
6958627 Asynchronous pipeline with latch controllers  
An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other...
Matches 1 - 50 out of 166 1 2 3 4 >