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7620926 |
Methods and structures for flexible power management in integrated circuits
Structures and methods of efficiently implementing power management in integrated circuits (ICs). An IC includes columns of logic blocks and columns of power management blocks (PMBs). The columns...
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7617409 |
System for checking clock-signal correspondence
A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving...
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7605612 |
Techniques for reducing power requirements of an integrated circuit
A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock...
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7602217 |
Level shifter circuit with pre-charge/pre-discharge
A level shifter circuit and method of operating therefor. The level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain....
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7602211 |
Semiconductor integrated circuit device
A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which...
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7599457 |
Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits
In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel...
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7592840 |
Domino circuit with disable feature
Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.
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7589565 |
Low-power multi-output local clock buffer
An improved circuit for reducing a capacitance load on a processor. The circuit includes a global clock circuit capable of producing a primary timing signal. The circuit further includes a local...
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7586334 |
Circuit arrangement and method for processing a dual-rail signal
The present invention relates to a circuit arrangement for processing a dual-rail signal, comprising data inputs for feeding at least one dual-rail data input signal, and respective data outputs...
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7583106 |
Clock circuitry
A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative...
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7583103 |
Configurable time borrowing flip-flops
Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a...
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7576568 |
Self-selecting precharged domino logic circuit
A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the precharge node to charge the...
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7571341 |
Method and system for fast frequency switch for a power throttle in an integrated device
The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.
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7560956 |
Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether...
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7557616 |
Limited switch dynamic logic cell based register
A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front...
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7557610 |
Columnar floorplan
An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes...
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7557606 |
Synchronization of data signals and clock signals for programmable logic devices
Techniques for synchronizing data signals and clock signals of a programmable logic device (PLD) are provided. In one example, a method includes preparing an initial configuration of the PLD...
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7551002 |
Method and apparatus for implementing balanced clock distribution networks on ASICs with voltage islands functioning at multiple operating points of voltage and temperature
A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage...
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7551001 |
Reconfigurable semiconductor integrated circuit and processing assignment method for the same
A plurality of logic element groups LEG 11 to LEG 33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element...
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7550997 |
4-level logic decoder
The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits with each decoding...
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7545178 |
Signal encoder and signal decoder
A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the...
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7535259 |
Clocked inverter, NAND, NOR and shift register
A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or...
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7528630 |
High speed flip-flop
A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second...
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7526017 |
Transmitting device, receiving device, transmission system, and transmission method
A transmitter LSI 1 transmits a source clock, transmission data, and a transmission sync signal indicating the timing of the transmission data to a receiver LSI for establishing transmission...
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7518408 |
Synchronizing modules in an integrated circuit
A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK,...
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7518401 |
Differential clock tree in an integrated circuit
A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal...
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7511535 |
Fine-grained power management of synchronous and asynchronous datapath circuits
A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least...
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7508237 |
Mainboard, electronic component, and controlling method of logic operation
A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a...
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7504857 |
Functional cells for automated I/O timing characterization of an integrated circuit
Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are...
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7499831 |
Timing closure monitoring circuit and method
An integrated circuit 1 comprises a timing closure monitoring circuit 2 . The timing closure monitoring circuit 2 comprises a duplicate path 19 , having the same characteristics as a logic...
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7498845 |
Power supply switching at circuit block level to reduce integrated circuit input leakage currents
Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one...
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7495476 |
Logic circuit, system for reducing a clock skew, and method for reducing a clock skew
A logic circuit includes a first flip-flop configured to include a first input terminal introducing a clock, a first output terminal supplying the clock and a first internal wiring connecting the...
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7493461 |
Dynamic phase alignment for resynchronization of captured data
A source synchronous external memory device returns data to a memory controller of an electronic device with its own clock signal, which allows the returned data to be captured with a high degree...
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7492192 |
Logic processing apparatus, semiconductor device and logic circuit
A logic processing circuit including a plurality of flip-flop including a front stage flip-flop and a rear stage flip-flop, a logic gate circuit network adapted to process data stored in the front...
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7483013 |
Semiconductor circuit, display device, and electronic appliance therewith
It is an object of the invention to provide a semiconductor circuit requiring less number of transistors included in the semiconductor circuit and accurately serving as a shift register without...
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7482837 |
System and method for combining signals on a differential I/O link
System and method for combining signals on a differential signal provided over a communication link. In one aspect, a system for providing a differential communication link includes a signal...
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7479915 |
Comparator architecture
A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in a source/emitter follower...
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7478256 |
Coordinating data synchronous triggers on multiple devices
System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media...
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7477068 |
System for reducing cross-talk induced source synchronous bus clock jitter
A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the...
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7466723 |
Various methods and apparatuses for lane to lane deskewing
Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more...
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7456651 |
On-die termination apparatus for semiconductor memory having exact comparison voltage characteristic and method of controlling the same
An on-die termination apparatus for a semiconductor memory according to the invention includes: a first D/A converting unit that outputs a first voltage corresponding to a first code; a first...
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7454589 |
Data buffer circuit, interface circuit and control method therefor
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
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7453288 |
Clock translator and parallel to serial converter
A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to...
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7443222 |
Dynamic clock control
An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from...
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7443205 |
Relatively low standby power
Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the...
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7439773 |
Integrated circuit communication techniques
An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level....
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7436861 |
Asynchronous control circuit with symmetric forward and reverse latencies
One embodiment of the present invention provides a control queue for an asynchronous circuit that includes a number of control modules coupled together linearly to form the control queue. These...
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7436220 |
Partially gated mux-latch keeper
Embodiments related to multiplexer latches (mux-latches) are presented herein.
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7436217 |
Methods and apparatus for serially connected devices
Apparatus and methods for processing a clock input signal with a clock regeneration circuit to provide a clock output signal for coupling to a cascaded device. The clock output signal has a period...
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7436211 |
Transparent latch circuit
The present invention provides a transparent latch circuit capable of performing a scan test in general scan design (GSD). In the transparent latch circuit a test signal is at a Low level during...
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