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7068074 Voltage level translator circuit  
A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for...
7068065 System and method for dynamic impedance matching  
An integrated circuit provides dynamic, on chip resistor trimming, including a digital control loop for stabilizing impedance matching among multiple devices communicatively linked over a data...
7068078 Data output driver  
A data output driver, for use in a semiconductor memory device, includes a pull-up driving unit, having N numbers of unit pull-up drivers and N numbers of pull-up resistors, turned on by selected...
7064582 Output buffer strength trimming  
Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a...
7053661 Impedance-matched output driver circuits having enhanced predriver control  
Impedance-matched output driver circuits utilize predriver circuits with analog control to provide enhanced operating characteristics. This analog control may be provided by an analog loop...
7053660 Output buffer circuit and control method therefor  
An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected...
7030644 Low reflection driver for a high speed simultaneous bidirectional data bus  
A low reflection driver is provided for a high speed simultaneous bi-directional transmission line/data bus which is designed such that units at both ends of the transmission line/data bus can...
7019559 Level shift circuit  
A level shift circuit including a first transistor circuit connected between a power supply line and a first node, a second transistor circuit connected between the power supply line and a second...
7012450 Transmitter for low voltage differential signaling  
A low-voltage differential signal driver includes, in part, a current sourcing circuit, a current steering circuit, and a current sinking circuit. The current steering circuit steers the current...
7009435 Output buffer with controlled slew rate for driving a range of capacitive loads  
Output buffer slew rate variation over variations in load capacitance is minimized by dividing output voltage transitions into distinct time and output current segments. During the first time...
7005886 Tristateable CMOS driver with controlled slew rate for integrated circuit I/O pads  
A novel output driver for an integrated circuit, and method for controlling the slew rate of output signals driven by the output driver, is presented. The output driver employs a delayed...
6998875 Output driver impedance controller  
An output driver impedance controller for controlling pull-down impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one...
6985006 Adjusting the strength of output buffers  
The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be...
6985008 Apparatus and method for precisely controlling termination impedance  
An impedance controller that controls termination impedance of at least one output based on a reference value including a programmable reference impedance generator, at least one termination logic...
6980019 Output buffer apparatus capable of adjusting output impedance in synchronization with data signal  
In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality...
6977525 Current driver circuit  
A current driver circuit has a current driver and a current compensation circuit. The current driver has a current source transistor connected to a power source potential level, while it is...
6967512 Multiphase-clock processing circuit and clock multiplying circuit  
In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1′ are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1 and an NMOS...
6947334 Semiconductor memory device capable of calibrating data setup time and method for driving the same  
There is provided a synchronous memory device, in which a data input setup timing is calibrated. The synchronous memory device includes: a data input unit for calibrating a timing of data inputted...
6922079 Output driver apparatus and method thereof  
A drive controller monitors a dynamic condition to determine when a transmission line impedance is to vary. In one embodiment, a specific bit pattern associated with a set of data lines can be...
6922076 Scalable termination  
In a first aspect, a first method is provided for providing multiple termination values using a plurality of binary termination signals. The first method includes the steps of (1) determining a...
6922194 Method and apparatus for maintaining load balance on a graphics bus when an upgrade device is installed  
An embodiment of a graphics device that maintains load balance on a graphics bus when an upgrade graphics device is installed is disclosed. The embodiment includes load balancing buffers for the...
6919738 Output buffer circuit, memory chip, and semiconductor device having a circuit for controlling buffer size  
An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a...
6909308 Increasing drive strength and reducing propagation delays through the use of feedback  
Techniques of increasing drive strength and reducing propagation delays of a digital logic circuit through the use of feedback are presented. Logic circuitry operative to receive an input signal...
6909306 Programmable multi-standard I/O architecture for FPGAS  
The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to...
6900663 Low voltage differential signal driver circuit and method  
Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's...
6894547 Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit  
An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving...
6882187 Line driving circuit  
A line driver and a method for driving a line are disclosed. The line driver includes a first current device configured to initiate a change in the state of the line and a second current device...
6876225 Input/output interfacing circuit, input/output interface, and semiconductor device having input/out interfacing circuit  
The current generating unit in the transmitter generates output currents in accordance with a plurality of logic values. The reference current generating unit in the receiver generates a plurality...
6873196 Slew rate control of output drivers using FETs with different threshold voltages  
A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by connecting transistors with differing threshold...
6864737 Methods and systems for limiting supply bounce  
Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making...
6864706 GTL+Driver  
A driver operable with two power supplies, and provides, among other things, a high data communication rate, stabilized operating parameters including voltage output high, voltage output low, and...
6864705 Output buffer with low power/ground bounce noise and method for operating the same  
A method for operating an output buffer for reducing a power/ground bounce noise while maintaining high transmission rate is disclosed. The method includes steps of providing a plurality of...
6859069 Methods and systems for providing load-adaptive output current drive  
Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired...
6859402 Circuit for lines with multiple drivers  
An apparatus may include at least a first transistor, a second transistor, and a circuit. The first transistor has a first control terminal coupled to receive a first dynamic data signal, and is...
6856178 Multi-function input/output driver  
A high-speed I/O driver includes circuitry that is configurable to meet single-ended and differential I/O signal standards. For one embodiment, the driver includes four input circuits that can be...
6847238 Output circuit and method for reducing simultaneous switching output skew  
An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit...
6844753 Output circuit of semiconductor integrated circuit device  
This invention provide a new and improved output circuit of a semiconductor integrated circuit device that enables output of a slew-rate waveform with a desired gradient without generating...
6836143 Seminconductor integrated circuit with termination circuit  
A semiconductor integrated circuit device which includes a termination circuit for terminating a bus line. An impedance control circuit controls impedance of the termination circuit in accordance...
6834004 Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout  
A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs...
6815979 Impedance control circuit for controlling multiple different impedances with single control circuit  
An impedance control circuit includes a reference voltage output circuit for outputting one of a plurality of reference voltages; a variable resistor; a comparator and a control circuit. The...
6809546 On-chip termination apparatus in semiconductor integrated circuit, and method for controlling the same  
Provided are an on-chip termination apparatus in a semiconductor integrated circuit, and a method for controlling the same. The on-chip termination apparatus is installed in a semiconductor...
6810458 Method and circuit for hot swap protection  
A hot swap protection circuit (40) for an integrated circuit being plugged into a powered-up system includes a first circuit (10) for detecting a hot swap condition, a second circuit (20) coupled...
6801062 Output circuit  
In a first and second logic circuit controlling a driver circuit of CMOS configuration having a plurality of output transistors connected in parallel, a delay fluctuation clock signal and a delay...
6798256 Resonant buffer apparatus, method, and system  
A buffer circuit includes a resonant circuit. An output of the resonant buffer circuit transitions once for three transitions on an input.
6794909 Output circuit of semiconductor device having adjustable driving capability  
In an output circuit of a semiconductor device, an output buffer circuit includes a P-channel MOS transistor and a resistor connected in series between a line of a power supply potential and an...
6794925 Cold spare circuit for CMOS output circuit  
A first cold spare circuit has first and second transistors, and a second cold spare circuit has third and fourth transistors. The first transistor has a gate controlled by a function of a first...
6788102 Transmitter with active differential termination  
The present invention relates to a transmitter for high speed communication systems, comprising a plurality, preferably two, drivers each having series terminating resistor, wherein the series...
6784719 Level shift circuit for transmitting signal from leading edge to trailing edge of input signal  
A level shift circuit encompasses a first transmission circuit configured to transmit a leading edge of an input signal, a second transmission circuit configured to transmit a trailing edge of the...
6777987 Signal buffer for high-speed signal transmission and signal line driving circuit including the same  
A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes...
6774677 Device for linking a processor to a memory element and memory element  
A device having a processor and a memory element positioned outside the processor, as well as a device for linking a memory element to a processor, and a memory element, are described, the...