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7057415 |
Output buffer compensation control
One or more characteristics of circuitry for an output buffer are identified relative to a reference a plurality of times to produce a sequence of results. One or more compensation signals for one...
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7049861 |
Reduced current input buffer circuit
There is provided an input buffer circuit that, in one embodiment, includes an input buffer adapted to draw an operating current, a first buffer enabling circuitry operatively coupled to the input...
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7049849 |
Signal transmission circuits that use multiple input signals to generate a respective transmit signal
A transmission circuit that conducts signals between integrated circuit devices includes a first driver circuit that generates a first transmit signal in response to first and second input signals,...
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7049847 |
Semiconductor device
A semiconductor device including a tristate buffer circuit, which includes, on an output stage, at least a first transistor (P 1 ) for pull-up driving and a second transistor (N 1 ) for pull-down...
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7046038 |
Upward and downward pulse stretcher circuits and modules
The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the...
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7046033 |
Termination enable: hardware and software controlled enable with detect
A method and circuit allows flexible control for termination of a signal line. The mode of operation of the circuit may be set manually or automatically. A software controller provides software...
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7043674 |
Systems and methods for facilitating testing of pads of integrated circuits
Methods for testing integrated circuits (ICs) are provided. An embodiment of a method comprises: electrically interconnecting automated test equipment (ATE) with the IC; providing at least one...
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7038491 |
Level shifter for wide range operation
A programmable level shifter. The programmable level shifter comprises a first P-type FET, a second P-type FET, a third P-type FET, a fourth P-type FET, a fifth P-type FET, a sixth P-type FET, a...
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7038493 |
Circuit for eliminating leakage current in signal transmission
A circuit ( 3 ) for eliminating leakage current in signals transmitted from a first electronic system ( 1 ) to a second electronic system ( 2 ) includes two circuit units. Each circuit unit...
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7034570 |
I/O cell configuration for multiple I/O standards
Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where...
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7030656 |
Low voltage differential signaling device with feedback compensation
A low voltage different signaling (LVDS) includes an LVDS transmitter and an LVDS receiver. The LVDS transmitter includes a feedback compensation circuit, which adjusts and stabilizes the analog...
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7030655 |
Memory interface system
The invention relates to a semiconductor memory device and, more particularly, to an interface system for a semiconductor memory device. The interface includes a transmitter capable of encoding...
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7023242 |
Method and circuit configuration for adapting the voltage level for the transmission of data
The invention relates to a method and to a circuit configuration for adjusting the voltage level for the electrical data transmission between a transmitting component and a receiving component of...
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7019555 |
Circuit for performing on-die termination operation in semiconductor memory device and its method
A circuit for performing an on-die termination operation includes a clock buffer for outputting first and second buffered clocks using an external clock and an external inverting clock applied...
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7012449 |
Input and output driver
An input and output driver is disclosed which includes comprising a DQ switch capable of reducing a total input capacitance Cin by electrically isolating an output driver from a DQ pad using the DQ...
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7009426 |
Data transmission/reception system
In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by...
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7005891 |
Data transmission circuit for universal serial bus system
The data transmission circuit generates the first and second data signals that are transferred respectively to first and second data lines after delaying or expanding a rising edge or a falling...
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7002377 |
Clock signal detection circuit and semiconductor integrated circuit using the same
A clock signal detection circuit is provided that can reliably detect whether or not a clock signal is supplied with a reduced circuit scale and reduced power consumption. The clock signal...
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6998870 |
Method and apparatus for impedance matching in systems configured for multiple processors
A method and apparatus for impedance matching in systems configured for multiple processors is disclosed. In one embodiment, a computer system includes a first processor socket and a second...
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6998873 |
Data input/output buffer and semiconductor memory device using the same
Provided is a data input/output buffer and a semiconductor memory device using the same. A transistor of a switching means or a logical element out of devices constituting a data input/output...
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6998880 |
Driver circuit
The invention relates to a driver circuit with
a circuit node ( 10 ), at least two first transistors (P 1 , P 2 ), the load sections of which are switched in series and connect the circuit...
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6994562 |
Apparatus for multiplex communication
In an apparatus for multiplex communication, a bus line constitutes a bus type network for connecting a plurality of terminal communication equipments. A plug-shaped terminating resistance device...
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6980773 |
Apparatus and method for bias compensation in line circuits
A transmission line circuit includes a line driver having first and second outputs coupled through a differential transmission line to first and second inputs of a line receiver. A first bias is...
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6975140 |
Adaptive data transmitter having rewriteable non-volatile storage
A data transmitter and transmitting method are provided in which an adaptive finite impulse response (FIR) driver has a plurality of taps to which coefficients having updateable values are applied....
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6972590 |
Data bus with separate matched line impedances and method of matching line impedances
A data bus for a printed circuit board is disclosed having a plurality of lines separated by a substrate. A method is also disclosed for creating a bus with a reduced reflection of signal energy at...
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6972589 |
Method for rapidly propagating a fast edge of an output signal through a skewed logic device
The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the...
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6972595 |
Electrical circuit
An electrical circuit assembly includes a node and an electrical circuit. The circuit draws a node point to a specific potential when and for as long as the node point is not drawn in any other way...
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6970015 |
Apparatus and method for a programmable trip point in an I/O circuit using a pre-driver
The invention enables the performance of the input and output stages of an I/O circuit to be modified after an IC is manufactured. In one embodiment, the I/O circuit includes an output driver,...
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6960938 |
Enhanced CMOS circuit to drive DC motors
An enhanced CMOS circuit to drive a DC motor is disclosed, in which a CMOS circuit is used to form a driver circuit of the DC motor, replacing a conventional BiCMOS for the part of the driver...
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6958621 |
Method and circuit for element wearout recovery
A recovery circuit and a method for employing the same are provided. The recovery circuit has a current driver and, preferably two pass-gates, a first pass-gate connected in series to the current...
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6956404 |
Driver circuit having a plurality of drivers for driving signals in parallel
In a driver circuit having a plurality of drivers for driving signals in parallel, the drivers are each connected to an input signal line for receiving a respective input signal and to an output...
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6956402 |
Multi-device system and method for controlling voltage peaking of an output signal transmitted between integrated circuit devices
A multi-device system and method for controlling voltage peaking of an output signal transmitted between input and output circuits of integrated circuit devices utilizes various electrical elements...
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6947335 |
Semiconductor device with an input/output interface circuit for a bus
There is provided a control circuit which instructs, using a control signal, validation and invalidation of operations of an input/output interface circuit suitable for a bus such as the IIC bus...
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6940311 |
Data transmission system
A data transmission system includes a first bus; a first bus master coupled to the first bus; a second bus master coupled to the first bus; a bus arbiter coupled to the first and second bus masters...
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6937060 |
Method and apparatus for implementing power control in multi-voltage I/O circuits
A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias...
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6933750 |
Buffer circuit, buffer tree, and semiconductor device
A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at...
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6930514 |
Method and apparatus for transferring data between data buses
Systems and methods for transferring data. A circuit transfers information between two buses using different signal voltage levels and multiplexes signals applied to the second bus over multiple...
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6924661 |
Power switch circuit sizing technique
An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power...
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6922071 |
Setting multiple chip parameters using one IC terminal
A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to...
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6919735 |
Skewed nor and nand rising logic devices for rapidly propagating a rising edge of an output signal
The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the...
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6919738 |
Output buffer circuit, memory chip, and semiconductor device having a circuit for controlling buffer size
An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a...
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6919742 |
Fast ethernet and ethernet driver
A driver circuit for driving a line in a network comprises first driving means for driving the line, second driving means for driving the line, and switching means for switching between the first...
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6914451 |
Adaptive level binary logic
A digital logic interface circuit makes use of a logic signal representative of a logic signaling level definition, to determine the logic swing amplitude of signals from a given source adopting...
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6903570 |
Bidirectional signal transmission circuit
A bidirectional signal transmission circuit includes: a buffer element for reducing the impedance of a signal line; a signal line disposed between input terminals in both ends of the bidirectional...
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6903577 |
Delay circuit
An input signal (SIN) is inverted by an inverter ( 101 ), and the inverted input signal is entered into a tri-state type inverter ( 104 ). An output portion of this inverter is connected via a...
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6903578 |
Logic isolator
A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic...
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6897685 |
Differential data transmitter
A differential data transmitter includes a first pre-driver configured to receive a differential data signal, a delay circuit configured to receive the differential data signal in parallel with the...
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6897681 |
Time division multiplexed serial bus with increased bandwidth
The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to connection to the input of the multiplexed...
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6894538 |
Expanding module for serial transmission
An expanding module for serial transmission between a chip and a plurality of interface units is disclosed. The module is comprised of a plurality of first OR gates and a plurality of second OR...
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6891398 |
Skewed falling logic device for rapidly propagating a falling edge of an output signal
The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the...
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