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7592838 Method for communicating data and clock signals and corresponding signal, transmitter and receiver  
A clock signal constituted by pulses with given frequency of repetition and a data signal is able to assume two logic levels are transmitted simultaneously on a two-wire line in the form of a...
7548092 Implementing logic functions with non-magnitude based physical phenomena  
An n-valued switch with n≧2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal...
7541836 Binary boolean output on input with more than two states  
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic...
7469016 Circuit for generating ternary signal  
A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each...
7403036 Interface circuit  
As a data bus control enable signal is set to “H,” a PMOS turns on when a bi-directional bus is not in use (i.e., when a data bus active signal is “L”), so that the bi-directional bus is...
7397690 Multi-valued digital information retaining elements and memory devices  
Discussed are models and methods to create stable binary and non-binary sequential devices including one or more logic functions of which an output signal is uniquely related to an input signal....
7385422 Tri-state output logic with zero quiescent current by one input control  
A voltage generating circuit, which generates tri-state logic output in accordance with high, low or floating of the input node, is proposed. The present voltage generating circuit includes: a...
7373569 Pulsed flop with scan circuitry  
In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected...
7355444 Single and composite binary and multi-valued logic functions from gates and inverters  
Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a...
7327162 Operations with logical states from a four voltage level signal  
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic...
7199611 System to temporarily modify an output waveform  
Systems and methods are disclosed for providing a temporarily modified output. A waveform control provides a control output that temporarily adjusts to an intermediate level between normal high and...
7183792 Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same  
A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having approximately an input threshold value for...
7157939 Quad state memory with converter feedback, transmission, and clock circuitry  
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic...
7053655 Multi-level driver stage  
An inventive driver stage for driving an output on one of n-levels, which are each spaced from each other by a voltage difference of ΔV, includes a plurality of field effect transistors for...
6963225 Quad state logic design methods, circuits, and systems  
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic...
6930513 Simultaneous bi-directional signal transmission system and semiconductor device therefor  
A simultaneous bi-directional signal transmission system includes a first semiconductor device, a second semiconductor device, and one or more transmission lines. The first semiconductor device...
6888765 Integrated circuit and method for testing same using single pin to control test mode and normal mode operation  
An integrated circuit including operational circuitry operable in response to at least one control signal asserted to an external node from an external source, and test circuitry coupled to the...
6842044 Glitch-free receivers for bi-directional, simultaneous data bus  
A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two...
6794899 On chip method and apparatus for transmission of multiple bits using quantized voltage levels  
Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without...
6714045 Static transmission of FAST14 logic 1-of-N signals  
A static output signal is generated using a static storage element ( 104 ) and transmitted to a NDL gate ( 110 ) over a transmission path ( 112 ) that is characterized by a user-specified...
6700406 Multi-valued logical circuit with less latch-up  
This three-valued inverter includes first and second P-channel MOS transistors connected in series between a line of a first power supply potential and an output node, and each having a gate...
6392445 Decoder element for producing an output signal having three different potentials  
The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The...
6377073 Structure and method for reduction of power consumption in integrated circuit logic  
A reduced power dissipation integrated circuit. Power dissipation within a CMOS circuit is reduced by substitution of multi-level buses with several thresholds for binary state buses with a single...
6333640 Asynchronous logic with intermediate value between data and null values  
A switching element and method for asynchronous logic switches an output signal according to a switching-logic relationship between or among input signals. Input signals may assume at least a DATA...
6211698 High speed interface apparatus  
The present invention discloses a much higher speed interface apparatus which comprises a data driving means for decoding two-bit data signals using them as inputs to output four-level data...
6208166 Circuit and method for implementing combinatorial logic functions  
A Transfer Logic Cell (TLC) circuit performing non-boolean logic elementary operations between a dual-rail input and a dual-rail output upon assertion of signals on at least one control terminal to...
6160437 Multiplexer for producing multi-level output signals  
The present invention discloses a multiplexer including that provides an output signal having a voltage range substantially equal to an input signal. The multiplexer further provides a breakdown...
6137310 Serial switch driver architecture for automatic test equipment  
A tristate circuit for driving three signal levels to a pin of a device-under-test is disclosed. The tristate circuit includes a driver having an output at a first signal level and adapted for...
6133754 Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)  
Circuit structure and resulting circuitry for multiple-valued logic. The circuit structure allows the design and fabrication of any r-valued logic function of n-places where r is an integer greater...
6040709 Ternary signal input circuit  
A ternary signal input circuit includes two inverters having opposite hysteresis characteristics, respectively, a NOR gate for producing an output signal indicative of an inversion of the logical...
6031390 Asynchronous registers with embedded acknowledge collection  
An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line...
5969540 Three-level detector without standby current  
A three-level detector is used to detect the state of a level input pertaining to a relatively-high level, a relatively-low level, or floating. The three-level detector comprises a first inverter,...
5917338 Area-efficient implication circuits for very dense Lukasiewicz logic arrays  
A one-diode circuit for negated implication (.about.➝) is derived from a 12-transistor Lukasiewicz implication circuit (➝). The derivation also yields an adjustable three-transistor implication...
5896541 Null convention register file  
A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL...
5841874 Ternary CAM memory architecture and methodology  
The present invention encompasses a method of storing ternary data that includes the steps of (1) initializing a conversion register by storing binary-to-ternary mask data in a conversion register;...
5828228 Null convention logic system  
A NULL convention logic element comprises an input, an output and a threshold switching circuit. The input receives NULL convention signals that are encoded onto a plurality of physical input...
5793816 Method of transferring data between subsystems of a computer system  
Data transmission arrangement for transmitting data between integrated circuit chips in a computer comprises a driver circuit having inputs connected to two discrete data bits. The driver circuit...
5731719 Phase detector for a ternary signal  
A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two...
5714891 Multiple-valued literal circuit using resonant tunneling diodes  
A multiple-valued literal circuit is implemented with resonant tunneling diodes (RTD). A number of RTD sections are connected in series with a current source. Current is tapped by a current bleeder...
5644253 Multiple-valued logic circuit  
There are provided n operation circuits in a multiple-valued logic circuit which receives plural multiple-valued input logic signals corresponding to respective numeral values and outputs a...
5612633 Circuit for simultaneously inputting and outputting signals on a single wire  
A configurable cellular array is provided having a 2-dimensional array of cells in which each cell in the array has at least one input and output connection at least one bit wide to its neighbours....
5610537 Trinary logic input gate  
A trinary input logic gate (25). A first output transistor (36) is coupled to a first voltage output (Vo1) and pulls the voltage output to a high voltage in response to a voltage input (VIN) below...
5598110 Detector circuit for use with tri-state logic devices  
A logic state detector that indicates a floating state of a tri-state logic circuit. The logic state detector generates first and second binary logic signals at a pair of output terminals. A first...
5563530 Multi-function resonant tunneling logic gate and method of performing binary and multi-valued logic  
A multi-function resonant tunneling logic gate is provided in which a resonant tunneling transistor (12) includes a first terminal, a second terminal, and a third terminal. A plurality of signal...
5498980 Ternary/binary converter circuit  
An integrated semiconductor circuit configuration includes one input of the circuit configuration for receiving a ternary input signal, and two outputs of the circuit configuration for supplying...
5483283 Three level high speed clock driver for an image sensor  
A high speed clock driver circuit for use with an area image sensor which has two horizontal shift registers is disclosed. Circuitry is provided which is responsive to the third level of one of the...
5459411 Wired-OR logic circuits each having a constant current source  
A wired-OR logic circuit has a plurality of logic circuit connected to a common signal line. Each of the plurality of logic circuits includes an output bipolar transistor for outputting a logical...
5450023 Interface circuit using a limited number of pins in LSI applications  
An interface circuit for reducing the number of data pins in an LSI circuit. The interface circuit, converts a multivalue input signal of a predetermined level into a binary value or converts a...
5153457 Output buffer with DI/DT and DV/DT and Tri-State Control  
An output buffer (12) is provided for producing an output signal varying between a voltage on a first lien (22) and a voltage on a second line (36). First output circuitry (3, 4) is provided for...
5126600 Truth value generating basic circuit suitable for analog inputs  
A truth value generating basic circuit according to the invention is characterized by having one or a plurality of basic function generator circuits (23, 24) which receive an analog applied input...
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