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7099395 Reducing coupled noise in pseudo-differential signaling systems  
A pseudo-differential signaling system uses a plurality of signal lines and a single, common reference voltage. Signal line voltages are interpreted only in comparison to the reference line...
6946875 Universal logic module and ASIC using the same  
A universal logic module that may have a reduced off-leak current in universal logic cells ( 100 ) not used as logic circuits has been disclosed. A universal logic module may include universal...
6882177 Tristate structures for programmable logic devices  
A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or...
6809550 High speed zero DC power programmable logic device (PLD) architecture  
A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell...
6670201 Manufacturing method of semiconductor device  
A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During...
6664806 Memory address and decode circuits with ultra thin body transistors  
A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder...
6552566 Logic array circuits using silicon-on-insulator logic  
Logic array circuits are formed on SOI substrates. The pull-down network ( 130 ) of the logic array circuit comprises NMOS transistors ( 125 ) and PMOS transistors ( 120 ) configured in series.
6384624 Logical operational circuit using two stage neumos circuits  
The present invention has as an object thereof to provide a logical operational circuit which is capable of realizing, with present semiconductor manufacturing technology, logical functions, the...
6346827 Programmable logic device input/output circuit configurable as reference voltage input circuit  
A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable,...
6222383 Controlled PMOS load on a CMOS PLA  
A programmable logic array (PLA) AND plane receives data input signals from input registers and generates corresponding minterms. The minterms are OR-ed together to form a sum of products, which...
6154049 Multiplier fabric for use in field programmable gate arrays  
A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of multiplier tiles. The CLEs can...
6124729 Field programmable logic arrays with vertical transistors  
A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a...
6111428 Programmable logic array  
There is provided a programmable logic array in which a precharge circuit is provided separately from precharge transistors. The precharge circuit can connect the one of wirings connecting memory...
6066959 Logic array having multi-level logic planes  
A logic array includes an AND plane, a first OR plane, and a second OR plane. The AND plane is adapted to receive a plurality of logic array inputs and provide a plurality of minterms. Each minterm...
5959465 Fast Nor-Nor PLA operating from a single-phase clock  
A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming...
5926039 Active load for an N channel logic network  
An active load (12) is provided for an N channel logic network (10). The active load (12) includes a P channel device (28) coupled to the output node (14) of the N channel network (10). A clock...
5872462 Programmable logic array and method for its design using a three step approach  
A PLA whose slowest product terms are located as close as possible to the true/complement generators or input buffers. The associated input buffers and product terms are partitioned into two or...
5867038 Self-timed low power ratio-logic system having an input sensing circuit  
A ratio-logic system having an input sensing device and a resetable delay device is disclosed. The input sensing device receives an input having a first logic state and a second input having a...
5852365 Variable logic circuit and semiconductor integrated circuit using the same  
A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned...
5821770 Option decoding with on-chip electrical fuses  
A method for varying the type of function selected on a chip (for example, after completion of manufacturing) may include the steps of providing predetermined fuse arrangements which individually...
5818261 Pseudo differential bus driver/receiver for field programmable devices  
A bus mechanism mitigates programmable device performance and power consumption issues by utilizing a small swing transmitter at the source end of an interconnect network and a high gain...
5751165 High speed customizable logic array device  
A very high speed customizable logic array device comprising: a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer...
5719505 Reduced power PLA  
A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one...
5666071 Device and method for programming high impedance states upon select input/output pads  
An integrated circuit incorporating programmable pullup and pulldown devices into each input/output (I/O) pad is described. Each I/O pad may be individually programmed to include a pullup or...
5617041 Method and apparatus for reducing coupling switching noise in interconnect array matrix  
In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory...
5610535 Programmable two-line, two-phase logic array  
A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal...
5587945 CMOS EEPROM cell with tunneling window in the read path  
A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate...
5568067 Configurable XNOR/XOR element  
A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is...
5539329 Programmable logic circuit w/neuron MOS transistors  
A semiconductor integrated circuit adaptable to any logic circuits using a common mask with the exception of a mask of metallic wirings so as to drastically improve performance of custom LSIs. The...
5502404 Gate array cell with predefined connection patterns  
A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10, 12, 14 with all such N-channel transistors coupled in series. A plurality of P-channel transistors 16, 18...
5495183 Level conversion circuitry for a semiconductor integrated circuit  
In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or...
5488317 Wired logic functions on FPGA's  
An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and...
5479369 Semiconductor integrated circuit device and semiconductor memory device  
In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the...
5452229 Programmable integrated-circuit switch  
A non-volatile, in-system programmable integrated-circuit switch has horizontal conductive lines and vertical conductive lines. A programmable interconnect cell including a floating gate transistor...
5446401 Synchronous dual word decoding using PLA  
A logic circuit arrangement for performing synchronous dual word decoding utilizing a programmable logic array which is formed with a reduced number of transistor counts. This is achieved by...
5444394 PLD with selective inputs from local and global conductors  
A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array...
5440182 Dynamic logic interconnect speed-up circuit  
A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, is disclosed. In one embodiment, a plurality of clocked dynamic logic circuits,...
5428255 Gate array base cell with multiple P-channel transistors  
A gate array base cell (100) performs logic and memory cell functions and comprises a first P-channel transistor (M1) for performing logic functions and having a first predetermined...
5424589 Electrically programmable inter-chip interconnect architecture  
A user-programmable inter-chip interconnect architecture, which may be used for providing programmable interconnections among a plurality of integrated circuits, is disclosed. A plurality of main...
5424654 Programmable macrocell circuit  
A digital logic circuit for use in or as a macrocell which can be programmed to operate as a flip-flop or as a latch, or to be transparent to a signal, and which also has programmable output...
5422581 Gate array cell with predefined connection patterns  
A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel...
RE34916 Method and circuitry for testing a programmable logic device  
A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into...
5406139 Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching  
An input buffer for utilization in a programmable logic device (PLD). The input buffer includes an inverter consisting of a PMOS pull up transistor one half the size of a corresponding NMOS pull...
5399924 Low current optional inverter  
A low power optional inverter uses P-channel and N-channel transistors in series as in a conventional CMOS inverter, but in one embodiment connects complementary signals to the sources of the...
5394103 Field programmable gate array  
A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small...
5384738 Semiconductor integrated circuit device  
A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS...
5367209 Field programmable gate array for synchronous and asynchronous operation  
A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and...
5338982 Programmable logic device  
A semiconductor integrated circuit capable of electrically writing functions according to this invention comprises a plurality of logical blocks capable of electrically writing functions and wire...
5336951 Structure and method for multiplexing pins for in-system programming  
A structure and method for in-system programming of a programmable logic device are provided. The in-system programming structure provides one dedicated pin for in-system programming function,...
5214327 Programmable logic device and storage circuit used therewith  
A programmable logic device comprises a data storage circuit for storing 1-bit control data and a MOS transistor which is switch controlled in accordance with stored data in the data storage...
Matches 1 - 50 out of 123 1 2 3 >