Matches 401 - 450 out of 1434 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >
Match Document Document Title
7142011 Programmable logic device with routing channels  
A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple...
7138826 Self-rewinding circuit  
A self-rewinding circuit includes a first block of combinatorial logic having a set of inputs including at least one input and a set of outputs including at least one output wherein a relationship...
7138828 FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same  
An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A...
7138820 System monitor in a programmable logic device  
Method and apparatus for a system monitor ( 20 ) embedded in a programmable logic device ( 10, 50, 60 ) are described. The system monitor ( 20 ) includes a dynamic reconfiguration port interface (...
7138829 Measuring input setup and hold time using an input-output block having a variable delay line  
A system and method for measuring the timing requirements of a sequential logic element of a programmable logic device. The sequential logic element has a first data terminal, an output terminal,...
7138827 Programmable logic device with time-multiplexed interconnect  
A PLD includes at least one portion of the programmable interconnect that can be time multiplexed. The time multiplexed interconnect allows signals to be routed on shared interconnect at different...
7135887 Programmable logic device multispeed I/O circuitry  
Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O...
7135888 Programmable routing structures providing shorter timing delays for input/output signals  
Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to...
7135890 SCL type FPGA with multi-threshold transistors and method for forming same  
A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering...
7137095 Freeway routing system for a gate array  
A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input...
7132853 Inter-tile buffer system for a field programmable gate array  
An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and...
7132851 Columnar floorplan  
An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes...
7132852 Routing architecture with high speed I/O bypass path  
Improved routing architectures including one or more high speed input/output (I/O) bypass paths are provided for use in, for example, programmable logic devices (PLDs) such as field programmable...
7129747 CPLD with fast logic sharing between function blocks  
Fast logic sharing is created using a feedback path from the output logic macrocell of one functional block to the product term inputs of another function block without going through an advanced...
7129743 Digital audio system on a chip  
A GPIO cell of a SOC functions, in a first state, to pass an output signal from one of plurality of modules of the SOC to a pin when an output enable signal is activated. The GPIO cell further...
7129745 Apparatus and methods for adjusting performance of integrated circuits  
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The...
7129749 Programmable logic device having a configurable DRAM with transparent refresh  
A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit...
7126214 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements  
A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable...
7126381 VPA interconnect circuit  
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The...
7126374 Multi-level routing architecture in a field programmable gate array having transmitters and receivers  
A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in...
7126375 Floor plan for scalable multiple level tab oriented interconnect architecture  
A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the...
7126372 Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration  
Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The...
7123052 Interconnection resources for programmable logic integrated circuit devices  
A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections...
7123050 Programmable array logic circuit employing non-volatile ferromagnetic memory cells  
A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is...
7119575 Logic cell with improved multiplexer, barrel shifter, and crossbarring efficiency  
Logic circuits that provide improved efficiency are described. In one general embodiment, this is accomplished by feeding outputs of LEs in the logic circuit to multiplexers that receive their...
7119576 Devices and methods with programmable logic and digital signal processing regions  
A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least...
7119574 Passage structures for use in low-voltage applications  
Enhanced passgate structures for use in low-voltage systems are presented in which the influence of V t on the range of signals passed by single-transistor passgates is reduced. In one...
7116131 High performance programmable logic devices utilizing dynamic circuitry  
A programmable logic device (PLD) includes dynamic lookup table (LUT) circuits, an interconnect structure implemented in either dynamic or static logic, and optional static logic circuits. Each...
7116130 Method and apparatus for effectively re-downloading data to a field programmable gate array  
A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of...
7117373 Bitstream for configuring a PLD with encrypted design data  
It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted...
7112993 Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an FPGA  
A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first...
7112992 Configuration shift register  
An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset...
7109748 Integrated circuits with reduced standby power consumption  
Integrated circuit standby power consumption may be reduced using a reverse-bias transistor control arrangement that reduces transistor leakage current. Integrated circuit transistors may be turned...
7111214 Circuits and methods for testing programmable logic devices using lookup tables and carry chains  
Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern...
7109746 Data monitoring for single event upset in a programmable logic device  
Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable...
7109751 Methods of implementing phase shift mask compliant static memory cell circuits  
Methods of implementing a static memory cell compliant with the requirements of phase shift masks. A phase shift compliant memory cell is generated by implementing a single bit line, two word...
7111273 Softpal implementation and mapping technology for FPGAs with dedicated resources  
A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several...
7109753 Programmable logic device with routing channels  
A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple...
7109744 Programmable termination with DC voltage level control  
Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of...
7109745 Configurable integrated circuit for use in a multi-function handheld device  
A configurable integrated circuit includes at least one general purpose input/output (GPIO) interface module, a first functional module, and a second functional module. The GPIO interface module...
7109747 Low power, high speed logic controller that implements thermometer-type control logic by utilizing scan flip-flops and a gated clock  
The power dissipation, logic complexity and chip area of a thermometer controller are all significantly reduced by utilizing a series of scan flip-flops that are connected together to form a...
7106099 Decision-feedback equalization clocking apparatus and method  
A decision feedback equalization (“DFE”) technique is suitable for use in a serializer-deserializer (“SERDES”) receiver in an integrated circuit (IC). The IC has a summing node coupled to a...
7102385 Dedicated input/output first in/first out module for a field programmable gate array  
A field programmable gate array architecture having a plurality of input/output pads comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output...
7102387 Periodic computation structure based on 1-input lookup tables  
A simplified implementation of molecular field programmable gate arrays described in U.S. Pat. No. 6,215,327 and U.S. Pat. No. 6,331,788, reducing the complexity in a tiled array template to that...
7102386 Reconfigurable electronic device having interconnected data storage devices  
A reconfigurable electronic device ( 100 ), e.g., a field programmable gate array (FPGA) or another type of complex programmable logic device (CPLD), has a first data storage device ( 120 ) and a...
7098690 Programmable I/O element circuit for high speed logic devices  
A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may...
7098691 Structured integrated circuit device  
A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a...
7098688 Regionally time multiplexed emulation system  
A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and...
7098687 Flexible routing resources in a programmable logic device  
In particular aspects, embodiments of the present invention provide a programmable logic device including routing paths from one routing resource to another via connections between outputs of...
7100130 Device for the emulation of designs for integrated circuits  
A device for the emulation of designs for integrated circuits having a receiving device for multiple programmable logic circuits, particularly FPGAs, and an electrical connection structure. The...
Matches 401 - 450 out of 1434 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >