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6653860 Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures  
An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base...
6650143 Field programmable gate array based upon transistor gate oxide breakdown  
A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and...
6633182 Programmable gate array based on configurable metal interconnect vias  
A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design...
6633179 Bidirectional signal control circuit  
A wire used for transferring bidirectional signals is divided into a plurality of sub line segments. These sub line segments are classified into groups. Further, bidirectional buffers are provided...
6631487 On-line testing of field programmable gate array resources  
A method of testing field programmable gate array (FPGA) resources and identifying faulty FPGA resources during normal on-line operation includes configuring an FPGA into a working area and an...
6631510 Automatic generation of programmable logic device architectures  
The invention consists of a new component called the Architecture Generation Engine added to the CAD system for implementing circuits into PLD architectures and for evaluating performances of...
6628140 Programmable logic devices with function-specific blocks  
A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in...
6625796 Apparatus and method for programming a set of programmable logic devices in parallel  
A method of configuring a set of programmable logic devices includes the step of partitioning a programming file into a set of programmable logic device configurations. A set of programmable logic...
6625794 Method and system for safe device reconfiguration  
A novel method and corresponding system are provided for safely reconfiguring a portion of a reprogrammable logic device. The method includes the steps of identifying the nets to be reprogrammed,...
6624654 Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets  
Methods for implementing a circuit in a programmable logic device (PLD) that protect the circuit from the effects of single event upsets. When routing nodes within the circuit using the...
6621293 Integrated circuit arrangement with feature control  
An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary...
6621297 Semiconductor device malfunction preventive circuit  
A semiconductor device malfunction preventive circuit S is disposed in a macrocell logic cell 1 of a semiconductor device 50 used in an electronic device 100 . A signal in an output pin 3 or...
6617876 Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers  
Structures and methods that reduce interconnect resource usage and routing delays in FPGAs by routing high fan-out signals on the CLB carry chains. In a first embodiment, a high fan-out signal...
6614261 Interconnection and input/output resources for programable logic integrated circuit devices  
A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions....
6615402 Interchangeable FPGA-gate array  
A test facilitating circuit is contained in a FPGA-GATE ARRAY. In the gate array chip there are disposed I/O cells, a boundary scan circuit, a controller and an internal circuit. The arrangement of...
6614260 System and method for dynamic modification of integrated circuit functionality  
Programmable circuit blocks and programmable interconnection blocks are utilized to effectively modify the functionality of a section of the IC. The use of a fixed ion beam machine or similar...
6608500 I/O architecture/cell design for programmable logic device  
An apparatus comprising an input/output circuit and a programmable logic device. The input/output circuit may be configured to (i) connect to an end of a bus and (ii) operate in one or more modes...
6609235 Method for providing a fill pattern for an integrated circuit design  
A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The...
6605961 Low voltage PLA's with ultrathin tunnel oxides  
Systems and methods for programmable logic arrays having depletion mode, non volatile p-channel floating gate transistors with ultra thin tunnel oxides are provided. The programmable logic arrays...
6605962 PLD architecture for flexible placement of IP function blocks  
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
6605959 Structure and method for implementing wide multiplexers  
A method and a structure provide in a programmable logic device wide multiplexers without increasing delay and the number of interconnections in an input routing resource over corresponding...
6603332 Configurable logic block for PLD with logic gate for combining output with another configurable logic block  
An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the...
6600959 Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays  
A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using...
6593771 Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC  
An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The...
6590416 Supply voltage independent ramp-up circuit  
A ramp-up circuit on an integrated circuit receives a relatively high program (erase) voltage for changing the program state of a memory cell. The ramp-up circuit gradually raises the program...
6590417 Cascadable bus based crossbar switch in a programmable logic device  
A configurable crossbar switching circuit within a programmable logic device capable of efficient, large scale switching and for cascading for implementing much larger switching functions. In one...
6590415 Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources  
A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of...
6583645 Field programmable optical arrays  
An FPGA is described using optical waveguides for routing signals through the FPGA. The routing is controlled electrically. Either coupling waveguides or resonant disks can be used for routing the...
RE38152 Logic synthesis method and semiconductor integrated circuit  
A semiconductor integrated circuit of registers and combinational logic circuits connected between the registers is generated by a top-down design technique. When performing the logic synthesizing...
6580289 Cell architecture to reduce customization in a semiconductor device  
A semiconductor device and method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the...
6577158 Interconnect circuitry for implementing bit-swap functions in a field programmable gate array and method of operation  
There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA. The FPGA comprises: 1)...
6573748 Programmable logic device with output register for specifying memory space during reconfiguration  
Described are programmable logic systems and methods in which programmable logic devices receive configuration data. In some embodiments, one or more input/output blocks of a programmable logic...
6573749 Method and apparatus for incorporating a multiplier into an FPGA  
One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one...
6563340 Architecture for implementing two chips in a package  
A device having two or more programmable logic devices within an assembly apparatus. A first programmable logic device may be configured to have (i) a first signal interface and (ii) a second...
6556043 Asynchronous latch design for field programmable gate arrays  
A programmable logic circuit is provided that solves glitch problems associated with asynchronous logic operations associated with conventional look-up tables by utilizing a preset dominant...
6549035 High density antifuse based partitioned FPGA architecture  
An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in...
6545504 Four state programmable interconnect device for bus line and I/O pad  
A one transistor, non-volatile programmable switch having four operating states for connection between circuit elements and passive elements including bus lines and input/output pads. The four...
6545505 Hybrid routing architecture for high density complex programmable logic devices  
A scalable routing architecture for high density programmable logic devices involves the utilization of a two-dimensional network of non-segmented routing channels to serve as global interconnects...
6543030 Computer-implemented conversion of combination-logic module for improving timing characteristics of incorporating integrated circuit design  
The timing characteristics of an integrated circuit design with an original combination-logic module can be potentially improved by moving an input signal with problematic timing in the original...
6543032 Method and apparatus for local resynthesis of logic trees with multiple cost functions  
Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are...
6542394 Field programmable processor arrays  
An integrated circuit has a field programmable circuit region arranged as a generally rectangular array of rows and columns of circuit areas. Some of the circuit areas each provide a respective...
6529038 Antifuse programming method  
A method for programming antifuses includes applying a programming pulse having a magnitude equal to the programming potential across the conductive electrodes of the antifuse such that the more...
6529041 System power control output circuit for programmable logic devices  
A power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (“normal”) output mode, or a high current power control mode. In one embodiment, the...
6525562 Programmable logic device capable of preserving state data during partial or complete reconfiguration  
A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the...
6526461 Interconnect chip for programmable logic devices  
A method and apparatus for interconnecting multiple programmable logic devices. In a preferred embodiment of the invention, an interconnect chip couples one programmable logic device to another...
6525563 Crosspoint switch circuit and switch cell electronic circuit  
The present invention relates to a technology of a crosspoint switch circuit applied to a cross-connect apparatus, an ADM or the like employed in an optical network. According to the present...
6526559 Method for creating circuit redundancy in programmable logic devices  
In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally...
6518787 Input/output architecture for efficient configuration of programmable input/output cells  
A programmable input/output memory architecture. The programmable input/output memory cells are disposed in two segments about the periphery of the chip. Each segment has two data buses for...
6515511 Semiconductor integrated circuit and semiconductor integrated circuit device  
A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes...
6515510 Programmable logic array with vertical transistors  
A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes...
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