Matches 651 - 700 out of 1428 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >
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6765409 Very low power, high performance universal connector for reconfigurable macro cell arrays  
A low-voltage programmable connector includes two separate paths. Each path includes a buffer and a pair of transmission gates whose control terminals receive the voltages supplied by a memory...
6762618 Verify scheme for a multi-level routing structure  
An efficient verify scheme for a multi-level routing structure is provided. For example, a two-level routing structure may have a second-level routing structure whose switch matrix is either...
6759871 Line segmentation in programmable logic devices having redundancy circuitry  
Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first...
6759869 Large crossbar switch implemented in FPGA  
A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch,...
6753696 Programmable optimized-distribution logic allocator for a high-density complex PLD  
A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic...
6750674 Carry chain for use between logic modules in a field programmable gate array  
A field programmable gate array comprising a plurality of logic modules each logic module having two clusters, said logic modules arranged in rows and columns. The logic module clusters having a...
6747481 Adaptive algorithm for electrical fuse programming  
This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of programming pulses. The solution is...
6748368 Proprietary core permission structure and method  
A programmable logic device includes a non-volatile permission memory block to enable a customer to utilize a proprietary core. In one embodiment, the core supplier designs its core to check for a...
6747479 Interface scheme for connecting a fixed circuitry block to a programmable logic core  
An apparatus comprising one or more configurable interface tiles. The configurable interface tiles may be configured to communicate one or more signals between one or more programmable logic cores...
6747480 Programmable logic devices with bidirect ional cascades  
A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions...
6748575 Programming programmable logic devices using hidden switches  
A programming tool for programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), supports the display of hidden-switch connections, in addition to the display of...
6744278 Tileable field-programmable gate array architecture  
An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing...
6744274 Programmable logic core adapter  
A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an...
6738858 Cross-bar matrix for connecting digital resources to I/O pins of an integrated circuit  
A matrix of routing cells forming a cross-bar decoder ( 310 ). Signal triplets are coupled through the cross-bar decoder ( 310 ) based on control by a microprocessor. A register ( 50 ) provide...
6735755 Cost saving methods using pre-defined integrated circuit modules  
This invention discloses a multiple-chip module (MCM) device supported on a semiconductor wafer. The MCM device includes a core module that has a plurality of logic circuits having a layer...
6731133 Routing structures for a tileable field-programmable gate array architecture  
A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of...
6727726 Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array  
The present system comprises a device and a method for increasing the performance and utilization in a field programmable gate array (FPGA). The device of the present system comprises an FPGA...
6717435 Programmable logic device and programming method  
Pin setting data for defining initial states of external pins of a programmable logic device (PLD) is transferred to the PLD to set all the external pins before logic setting data for the PLD is...
6718465 Reconfigurable inner product processor architecture implementing square recursive decomposition of partial product matrices  
A reconfigurable processor architecture based on unique square recursive order decomposition of partial product matrices is described. This architecture can be easily reconfigured by taking...
6717436 Reconfigurable gate array  
The invention relates to an FPGA (field programmable gate array) with a plurality of functional blocks. An interface enables data and address communication between a processor and the FPGA. The...
6714041 Programming on-the-fly (OTF)  
A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data...
6710625 Semiconductor integrated circuit having a gate array structure  
In a semiconductor integrated circuit having a gate array structure, within a cell, isolation transistors are disposed in series between an intra-cell gate output terminal and an intra-cell power...
6710621 Programmable power supply for field programmable gate array modules  
A module standard for FPGAs is provided in which power supply voltages for daughtercards are not fixed in advance. Instead programmable power supplies are provided and a method is provided in which...
6710620 Bus interface for I/O device with memory  
An electronic system is provided. The electronic system includes a logic device and at least one input/output interface coupled to the logic device. The electronic system further includes an...
6710623 Cascadable bus based crossbar switching in a programmable logic device  
A configurable crossbar switching circuit within a programmable logic device capable of efficient, large scale switching and for cascading for implementing much larger switching functions. In one...
6707314 Integrated circuit device, electronic equipment, and method of placement of an integrated circuit device  
A macrocell MC 1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O...
6707315 Registered logic macrocell with product term allocation and adjacent product term stealing  
A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an...
6703859 Programmable logic device and method of controlling clock signal thereof  
An object of the present invention is to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a...
6703860 I/O block for a programmable interconnect circuit  
A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may programmably...
6701500 Logic circuit module, method for designing a semiconductor integrated circuit using the same, and semiconductor integrated circuit  
A logic circuit module is used for designing a semiconductor integrated circuit using an FPGA (Field Programmable Gate Array) or a short-term gate array. Provided that a seventh input terminal of...
RE38451 Universal logic module with arithmetic capabilities  
A universal logic module for use in a programmable logic device, capable of generating all logical functions of three variables or less. The universal logic module also implements a full adder with...
6696855 Symmetric logic block input/output scheme  
A programmable logic device includes a plurality of clusters of logic elements. Each of the clusters may include a respective programmable interconnect matrix with each of the logic blocks of each...
6696856 Function block architecture with variable drive strengths  
Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The...
6693454 Distributed RAM in a logic array  
Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of...
6690195 Driver circuitry for programmable logic devices  
Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connections. Instances of the generalized...
6691267 Technique to test an integrated circuit using fewer pins  
A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this...
6680871 Method and apparatus for testing memory embedded in mask-programmable logic device  
In a mask-programmable logic device having embedded memory blocks, which device cannot be reconfigured for testing like a full programmable logic device, the embedded memory blocks are tested by...
6674303 Programmable input/output cell with bidirectional and shift register capabilities  
An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a...
6670826 Configurable logic block with a storage element clocked by a write strobe pulse  
A configurable logic block for a programmable logic device includes a storage element having a latch clocked by a write strobe pulse. The storage element uses a write strobe signal and, optionally,...
6670825 Efficient arrangement of interconnection resources on programmable logic devices  
Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be...
6667636 DSP integrated with programmable logic based accelerators  
A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are...
6667634 Multi-option setting device for a peripheral control chipset  
A multi-option setting device is provided for use in association with a connecting pin of a chipset for allowing user-selection from more than two setting options to set the chipset to perform one...
6668237 Run-time reconfigurable testing of programmable logic devices  
Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time...
6664807 Repeater for buffering a signal on a long data line of a programmable logic device  
A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset...
6664808 Method of using partially defective programmable logic devices  
FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a...
6664806 Memory address and decode circuits with ultra thin body transistors  
A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder...
6661254 Programmable interconnect circuit with a phase-locked loop  
A programmable interconnect circuit includes a phase-locked loop configured to provide an internal clock signal to I/O cells in the programmable interconnect circuit such that registers in the I/O...
6657458 Output buffer with feedback from an input buffer to provide selectable PCL, GTL, or PECL compatibility  
An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL,...
6657457 Data transfer on reconfigurable chip  
A reconfigurable chip having reconfigurable elements uses an interconnection system which reduces the maximum signal rise and fall time. In one embodiment, the maximum rise and fall time is reduced...
6653861 Multi-level routing structure for a programmable interconnect circuit  
A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may have a partially...
Matches 651 - 700 out of 1428 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >