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6861871 Cascaded logic block architecture for complex programmable logic devices  
Cascadable logic block architectures are disclosed for programmable logic devices, such as for high density and high performance complex programmable logic devices. The logic block architectures...
6859065 Use of dangling partial lines for interfacing in a PLD  
A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing...
6859066 Bank-based input/output buffers with multiple reference voltages  
A bank of input/output buffers are configured such that each input buffer in the bank may select from a plurality of voltage references during single-ended operation. Similarly, the pad associated...
6856167 Field programmable gate array with a variably wide word width memory  
A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and...
6856170 Clock signal transmission circuit  
A clock generator ( 10 a ) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control...
6853215 Programmable I/O element circuit for high speed logic devices  
A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may...
6847228 Carry logic design having simplified timing modeling for a field programmable gate array  
A configurable logic block (CLB) slice is provided that includes a single path for a carry input signal to propagate through the CLB slice as a carry output signal. This single path includes a...
6847227 Methods and apparatus for reconfiguring programmable devices  
There is disclosed a method for reconfiguring one or more programmable devices comprising the steps of: providing a datastream comprising one or more identification portions; loading data...
6844756 Configurable dedicated logic in PLDs  
An apparatus comprising one or more logic circuits. The logic circuits may be configured to provide computation. The one or more logic circuits generally comprise dedicated logic within a...
6844757 Converting bits to vectors in a programmable logic device  
A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used...
6842039 Configuration shift register  
An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset...
6842040 Differential interconnection circuits in programmable logic devices  
At least some of the interconnection signaling on a programmable logic device (“PLD”) is by differential signaling using differential driver circuitry to apply differential signals to a pair of...
6838903 Block connector splitting in logic block of a field programmable gate array  
A logic block in a field programmable gate array comprises a plurality of clusters of logic devices. At least one of the logic devices in each of the clusters has an input or an output. A first set...
6839888 Method for implementing bit-swap functions in a field programmable gate array  
There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA. The FPGA comprises: 1)...
6838904 Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation  
Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing...
6833730 PLD configurable logic block enabling the rapid calculation of sum-of-products functions  
A variety of CLB architectures enable the efficient implementation of sum-of-products functions in a PLD. Output signals from each lookup table (LUT) in a CLB are routed directly to a dedicated OR...
6831480 Programmable logic device multispeed I/O circuitry  
Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O...
6828822 Apparatus and methods for shared memory interfaces in programmable logic devices  
A programmable logic device (PLD) includes a memory controller. The memory controller includes a first controller that communicates via a shared interface with a first memory external to the PLD....
6828824 Heterogeneous interconnection architecture for programmable logic devices  
An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with...
6825689 Configurable input/output interface for a microcontroller  
A configurable input/output interface for a microcontroller. The present invention is an input/output (I/O) pin with a configurable interface to a microprocessor, and to a global mapping which...
6822477 Integrated circuit and associated design method using spare gate islands  
An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a...
6819135 Fast signal conductor networks for programmable logic devices  
A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A...
6819133 System and method for protecting configuration data for a programmable execution unit  
A system for protecting configuration data of a programmable execution unit (PEU) comprises a programmable array and programming logic. The programming logic is configured to receive configuration...
6816919 Method and system for configuring input/output points  
A control circuit for configuring at least one I/O module connector pin is provided. The circuit includes at least one port controlling a configuration of the at least one pin.
6815981 Programmable logic array integrated circuit devices  
A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns....
RE38651 Variable depth and width memory device  
A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address...
6812731 Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices  
Structures and methods for generating high reliability designs for PLDs on which single event upsets have minimal impact. When standard triple modular redundancy (TMR) methods are used in PLDs, a...
6812738 Vector routing in a programmable logic device  
A PLD is disclosed that uses vector routing between components. A vector routing path is coupled between the components and includes a group of wires for routing a group of bits as one vector so...
6809552 FPGA lookup table with transmission gate structure for reliable low-voltage operation  
A lookup table (LUT) for a field programmable gate array (FPGA) is designed to operate reliably at low voltage levels. The low-voltage LUT uses CMOS pass gates instead of unpaired N-channel...
6809551 Method of optimizing routing in a programmable logic device  
A method of routing input signals in a programmable logic device (PLD) is disclosed. In a PLD having a PLD domain and a vector domain, input signals from the PLD domain are typically routed to the...
6809550 High speed zero DC power programmable logic device (PLD) architecture  
A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell...
6806730 Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity  
An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least...
6800884 Inter-tile buffer system for a field programmable gate array  
The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate...
6798239 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry  
Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions...
6798242 Programmable logic device with hierarchical interconnection resources  
A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal...
6794897 High density antifuse based partitioned FPGA architecture  
An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in...
6791355 Spare cell architecture for fixing design errors in manufactured integrated circuits  
A fully self-sufficient configurable spare gate cell that has two types of inputs: a functional input bus and an equation input bus, whereby the spare gate cell can be transformed into any sum of...
6792588 Faster scalable floorplan which enables easier data control flow  
A floorplan for a reconfigurable chip uses slices adjacent to each of four corners of a region, each of the slices including tiles that contain multiple reconfigurable functional units including...
6788111 One cell programmable switch using non-volatile cell  
A one transistor, non-volatile programmable switch comprises a first node and a second node coupled with corresponding circuit elements in an integrated circuit. A single, non-volatile programmable...
6788104 Field programmable logic device with efficient memory utilization  
A field programmable logic device includes at least two independently configurable embedded memory structures. The memory structures may differ in at least one parameter, such as memory size,...
6788097 Security improvements for programmable devices  
A programmable logic device includes a function block to generate a power control signal that is distributed on a rail to selectively power down various components on the device. The rail is...
6788101 Programmable interface circuit for differential and single-ended signals  
A programmable interface circuit is disclosed, in accordance with one embodiment, which supports differential and single-ended signaling. For example, an input buffer within the programmable...
6781475 Transmission lines arrangement  
A transmission lines arrangement comprising a first plurality of transmission lines each transmission line having an effective characteristic impedance. The arrangement further comprises a second...
6781407 FPGA and embedded circuitry initialization and processing  
Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions...
6777979 FIFO memory architecture  
A FIFO coordinates with registers of a programmable semiconductor device, wherein the registers are clocked according to an internal clock and words are written into the FIFO according to a write...
6779168 Magnetoresistive memory for a complex programmable logic device  
The present invention is directed to magnetoresistive memory and data storage devices. A system for providing distributed functionality in an electronic environment includes a plurality of...
6774672 Field-programmable gate array architecture  
A field-programmable gate array (FPGA) is disclosed. A two-by-two array of FPGA tiles is surrounded by a JTAG interface, a Configuration interface and a BIST interface. Each interface is located...
6774669 Field programmable gate array freeway architecture  
The disclosed system relates to a freeway routing system and a fast-freeway routing system for a field programmable gate array. The field programmable gate array comprises a two by two array of...
6774670 Intra-tile buffer system for a field programmable gate array  
The invention relates to an intra-tile buffering system for a field programmable gate array. The field programmable gate array comprises a field programmable gate array tile comprising a number of...
6774671 Multi-purpose transistor array  
The addition of an array of transistors through areas of the circuit where active devices normally don't exist, such as under routing channels. By connecting this array of transistors such that the...
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