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6934927 Turn architecture for routing resources in a field programmable gate array  
An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery....
6933547 Memory cell for modification of default register values in an integrated circuit chip  
A memory cell circuit for modification of a default register value in an integrated circuit chip, which includes a plurality of metal layers and first and second supply potentials. The circuit...
6930511 Array of programmable cells with customized interconnections  
A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections...
6924661 Power switch circuit sizing technique  
An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power...
6922078 Programmable logic device with enhanced wide and deep logic capability  
A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may form product terms of a fixed input width. The cluster is configured to provide input...
6919736 Field programmable gate array having embedded memory with configurable depth and width  
A field programmable gate array (FPGA) has plural columns of run-time memory provided in each of one or more partitions. Each column of run-time memory has a plurality of configurable memory blocks...
6917219 Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice  
The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that...
6914449 Structure for reducing leakage current in submicron IC devices  
A technique for reducing leakage current in static CMOS devices by adding additional transistors in series between selected inverters or logic gates and ground or power. NMOS and PMOS transistors...
6911840 Integrated circuit with overclocked dedicated logic circuitry  
An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal...
6911842 Low jitter clock for a physical media access sublayer on a field programmable gate array  
A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality...
6907595 Partial reconfiguration of a programmable logic device using an on-chip processor  
A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration...
6903571 Programmable systems and devices with multiplexer circuits providing enhanced capabilities for triple modular redundancy  
Programmable systems and devices that include programmable multiplexers designed to minimize the impact of single event upsets (SEUs) on triple modular redundancy (TMR) circuits. In a programmable...
6903573 Programmable logic device with enhanced wide input product term cascading  
A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce...
6903574 Memory access via serial memory interface  
Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial...
6903575 Scalable device architecture for high-speed interfaces  
An architecture is disclosed to provide high-speed input/output interface capabilities for programmable devices. One or more configurable input/output circuits are situated between the input/output...
6900660 IC with digital and analog circuits and mixed signal I/O pins  
An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled...
6900659 Methods and apparatus for loading data into a plurality of programmable devices  
There is disclosed a method for loading data into a plurality of programmable devices connected in parallel to one or more data lines comprising the steps of: enabling a first programmable device...
6897679 Programmable logic array integrated circuits  
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the...
6897677 Programmable power supply system  
A module standard for integrated circuit such as FPGAs is provided in which power supply voltages for daughtercards are not fixed in advance. Instead programmable power supplies are provided and a...
6894532 Programmable logic arrays with ultra thin body transistors  
Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane...
6894534 Dynamic programmable logic array that can be reprogrammed and a method of use  
A dynamic PLA (DPLA) that combines registers and dynamic PLA to make the array “reprogrammable” after the array is built is disclosed. The DPLA comprises at least one logic plane; and at least...
6894530 Programmable and fixed logic circuitry for high-speed interfaces  
Systems and methods are disclosed for programmable logic devices requiring a high-speed input/output interface. Hard-macro circuits that are configurable, scalable, and cascadable complement the...
6891397 Gigabit router on a single programmable logic device  
Apparatus for network and system on a single programmable logic device is described. The programmable logic includes port modules. The port modules have configurable logic configured to process...
6888372 Programmable logic device with soft multiplier  
A programmable logic device is provided which includes a multi-port RAM block with a first port including first address registers and first data registers and with a second port including second...
6888371 Programmable interface for field programmable gate array cores  
A programmable interface for FPGA cores embedded in an integrated circuit. The interface has an interconnect multiplexer (which includes demultiplexers) connected to the FPGA core and other...
6888374 FPGA peripheral routing with symmetric edge termination at FPGA boundaries  
An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are...
6886070 Multiple user interfaces for an integrated flash device  
A memory device having multiple interfaces is described. The memory device may be configured to operate with different interfaces using configuration circuitry in the device that enables switching...
6886092 Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion  
A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code....
6885219 Programmable driver for an I/O pin of an integrated circuit  
A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits...
6882176 High-performance programmable logic architecture  
A programmable logic device architecture. This programmable logic architecture includes a first logic block ( 425 ) containing programmable logic elements for performing logic functions. The...
6879272 Method and apparatus for controlling data output frequency  
Broadly speaking, a method and corresponding apparatus is provided for controlling a data output rate of an electronic device. More specifically, the method and corresponding apparatus enables an...
6879185 Low power clock distribution scheme  
An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an...
6879183 Programmable logic device architectures with super-regions having logic regions and a memory region  
A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a...
6880144 High speed low power bitline  
A circuit for controlling a bitline during a memory access operation is provided. The circuit includes a plurality of sub-arrays with each sub-array having a plurality of memory cells. Each of the...
6879184 Programmable logic device architecture based on arrays of LUT-based Boolean terms  
Multiple product terms (PTs) are combined with a multiple-input look-up table (LUT) to form a LUT-based Boolean term (LBT) that generates a Boolean output. Multiple LBTs are combined with one or...
6876228 Field programmable gate array  
It is one object of the present invention to provide an FPGA for which the configuration time and the time required for rewriting connection information and logic structure information can be...
6876227 Simplifying the layout of printed circuit boards  
A method of simplifying the layout of a printed circuit board is disclosed that enables an integrated circuit to modify—after the integrated circuit is manufactured—which pads transport which...
6874107 Integrated testing of serializer/deserializer in FPGA  
A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at...
6870397 Input/output circuit with user programmable functions  
The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods. The present invention provides a signal follower circuit...
6870398 Distributed memory and logic circuits  
Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect...
6870394 Controlled input molecular crossbar latch  
A molecular crossbar latch is provided, comprising two control wires and a signal wire that crosses the two control wires to form a junction with each control wire. The latch further includes a...
6867616 Programmable logic device serial interface having dual-use phase-locked loop circuitry  
In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general...
6864714 PLDs providing reduced delays in cascade chain circuits  
The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select...
6864710 Programmable logic device  
A programmable logic device comprising one or more horizontal routing channels, one or more vertical routing channels, and a logic element. Each logic element may be configured to connect between...
6864709 Cross point switch with serializer and deserializer functions  
A programmable switch of three or more ports, each port having data lines separate from lines sharing control and addressing. The programmable switch includes internal logic control and electronic...
6864712 Hardening logic devices  
The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock...
6864713 Multi-stage interconnect architecture for complex programmable logic devices  
Systems and methods are disclosed for providing a multi-stage interconnect architecture, such as for high density and high performance complex programmable logic devices. As an example, a first...
6864711 Programmable array logic circuit whose product and input line junctions employ single bit non-volatile ferromagnetic cells  
A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is...
6861870 Dynamic cross point switch with shadow memory architecture  
The fuse points within a programmable AND array may be programmed with configuration signals to select for logical signals to form product term outputs in a logic mode. In a switch mode, a subset...
6861868 High speed interface for a programmable interconnect circuit  
A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route...
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