Patents in Class 326/40

Matches 1 - 50 out of 661

Match	Document	Document Title
1	7619441	Apparatus for interconnecting stacked dice on a programmable integrated circuit An apparatus for interconnecting stacked dice on a programmable integrated circuit is described. In one example, an integrated circuit die comprises a programmable integrated circuit that includes...
2	7609085	Configurable integrated circuit with a 4-to-1 multiplexer Some embodiments provide a configurable integrated circuit with a tile. The tile has a first input multiplexer (IMUX), a second IMUX, and a look up table (LUT). The first IMUX is configured as a...
3	7603599	Method to test routed networks Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources...
4	7602534	Interface circuit device and printing apparatus A CPU and an image memory are provided in a printing apparatus. An interface circuit device for inputting/outputting signals representing image data is interposed between the CPU and the image...
5	7598769	Apparatus and method for a programmable logic device having improved look up tables A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2 N configuration bit...
6	7592834	Logic block control architectures for programmable logic devices In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one...
7	7589651	Flexible signal detect for programmable logic device serial interface A serial interface for a programmable logic device (PLD) uses an analog-to-digital converter (ADC) in place of conventional signal detect and receiver detect circuitry. A separate ADC can be used...
8	7589556	Dynamic control of memory interface timing Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and...
9	7587537	Serializer-deserializer circuits formed from input-output circuit registers Input-output circuitry for integrated circuits such as programmable logic device integrated circuits is provided. The input-output circuitry can be configured to operate in a single-ended data mode...
10	7586327	Distributed memory circuitry on structured application-specific integrated circuit devices A logic module for a structured ASIC is mask-programmable to perform any of a plurality of logic functions or to alternatively function as two static random access memory (“SRAM”) cells. Most...
11	7584447	PLD architecture for flexible placement of IP function blocks In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
12	RE40894	Sample and load scheme for observability internal nodes in a PLD A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes...
13	7579865	Selective loading of configuration data into configuration memory cells In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of...
14	7576562	Diagnosable structured logic array A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection...
15	7576561	Device and method of configuring a device having programmable logic A method of configuring a device having programmable logic is disclosed. The method comprises storing instructions in the device; selecting between one of the instructions stored in the device and...
16	7573295	Hard macro-to-user logic interface A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first...
17	7573292	Pre-programmed integrated circuit including programmable logic A system for providing a pre-programmed integrated circuit including programmable logic, and method for providing same. The system includes: nonvolatile memory capable of having first data stored...
18	7570120	Multichannel memory-based numerically controlled oscillators A multichannel numerically controlled oscillator is provided. The multichannel numerically controlled oscillator has a dual port memory. An output function generation lookup table in the dual port...
19	7570076	Segmented programmable capacitor array for improved density and reduced leakage A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal ( 100 ), a plurality of circuit elements ( 322,...
20	7557604	Input circuit for mode setting An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode...
21	7551002	Method and apparatus for implementing balanced clock distribution networks on ASICs with voltage islands functioning at multiple operating points of voltage and temperature A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage...
22	7548095	Isolation scheme for static and dynamic FPGA partial programming An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are...
23	7548091	Method and apparatus to power down unused configuration random access memory cells A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A...
24	7545168	Clock tree network in a field programmable gate array A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a...
25	7545167	Configurable IC with interconnect circuits that also perform storage operations Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing...
26	7538579	Omnibus logic element Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use...
27	7538577	System and method for configuring a field programmable gate array A mechanism within an electronic system for adapting a field programmable gate array (FPGA) to a flash memory device that supports a synchronous serial peripheral interface (SPI) by coupling a...
28	7538574	Transparent field reconfiguration for programmable logic devices In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having...
29	7535253	Register data retention systems and methods during reprogramming of programmable logic devices Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with...
30	7532032	Configurable circuits, IC's, and systems Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable...
31	7525343	Method and apparatus for accessing internal registers of hardware blocks in a programmable logic device A method and apparatus for accessing internal registers of hardware blocks in a programmable logic device (PLD) are described. An aspect of the invention relates to a method of accessing at least...
32	7525340	Programmable logic device architecture for accommodating specialized circuitry A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized...
33	7518400	Barrel shifter implemented on a configurable integrated circuit Some embodiments provide a barrel shifter on a configurable integrated circuit (IC). The barrel shifter has a first set of tiles and a second set of tiles with configurable circuits. The barrel...
34	7518397	Chip with in-circuit programability A circuit for enabling an IC having a normal mode for performing normal functions and a program mode for programming settings of the IC to use same pins in both modes. The circuit includes an input...
35	7511641	Efficient bitstream compression According to one embodiment of the invention, a method of generating a compressed configuration bitstream for a programmable logic device comprises encoding the most-prevalent data word within the...
36	7504857	Functional cells for automated I/O timing characterization of an integrated circuit Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are...
37	7502378	Flexible wrapper architecture for tiled networks on a chip A wrapper organization and architecture for networks on a chip employing an optimized switch arrangement with virtual output queuing and a backpressure mechanism for congestion control.
38	7501854	True/complement generator having relaxed setup time via self-resetting circuitry An integrated circuit includes a data node, an output node, and set logic coupling to the data node to the output node. The set logic changes a state of the output node in response to a change in...
39	7498839	Low power zones for programmable logic devices An integrated circuit device such as a PLD is divided into a plurality of logic blocks, each including one or more resources of the device. The device includes a plurality of switch elements and a...
40	7495473	Non-volatile look-up table for an FPGA A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer...
41	7492187	Circuit arrangement for supplying configuration data in FPGA devices A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output...
42	7492184	Programmable logic device and method for designing the same The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic device 101 formed from programmable logical...
43	7489164	Multi-port memory devices A semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element, wherein reading the generated...
44	7489163	FPGA powerup to known functional state A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic...
45	7486111	Programmable logic devices comprising time multiplexed programmable interconnect Time-multiplexed interconnect structures, timing optimization techniques and software tools for said structures, for programmable semiconductor ICs is disclosed. A first aspect is a programmable...
46	7486109	Programmable logic device The PLD that can change the number of input lines and the number of rail between the memories for logic according to the objective logic function, and to which the optimum design can be done to...
47	7482834	Programmable multiplexer An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports...
48	7477072	Circuit for and method of enabling partial reconfiguration of a device having programmable logic A circuit for enabling partial reconfiguration of memory elements of a device having programmable logic is described. The circuit comprises a block of memory cells comprising a look-up table of a...
49	7463060	Programmable logic device and method of testing A programmable logic device may comprise a plurality of programmable resources and non-volatile configuration memory to store configuration data by which to configure the programmable resources....
50	7459931	Programmable logic devices with transparent field reconfiguration Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes...

Matches 1 - 50 out of 661

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