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7317329 Lookup table circuit  
The present invention provides a LUT circuit that can simultaneously determine the corresponding output values of a plurality of input values. The LUT circuit of the present invention includes a...
7312633 Programmable routing structures providing shorter timing delays for input/output signals  
Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to...
7312630 Configurable integrated circuit with built-in turns  
Some embodiments provide a configurable integrated circuit (“IC”) with a configurable node array. A configurable node array may include configurable nodes arranged in rows and columns. It may...
7310003 Configurable IC with interconnect circuits that have select lines driven by user signals  
Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of...
7307450 Programmable logic block for designing an asynchronous circuit  
A programmable logic block for an asynchronous circuit design is disclosed. After a programmable setup, the logic block not only has the processing function of common devices, but also communicates...
7304497 Methods and apparatus for programmably powering down structured application-specific integrated circuits  
Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that...
7305335 Permanent three-pole independent pole operation recloser simulator feature in a single-pole trip capable recloser control  
Disclosed is a permanent recloser simulator feature for use in a single-pole trip capable recloser control. The permanent recloser simulator feature includes a first logic circuit capable of...
7304499 Distributed random access memory in a programmable logic device  
Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user...
7292064 Minimizing timing skew among chip level outputs for registered output signals  
A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads...
7292062 Distribution of signals throughout a spine of an integrated circuit  
A system and method for distributing signals throughout an integrated circuit (IC). The system comprises a transmitter unit and a plurality of receiver units. The transmitter unit combines a...
7288957 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array  
The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing...
7282950 Configurable IC's with logic resources with offset connections  
A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of...
7276935 Input buffer with selectable threshold and hysteresis option  
An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger...
7277920 Implementing applications requiring access to multiple files  
The control flow underlying an application is represented in the form of a FSM (Finite State Machine) containing multiple states, transitions between states, and tasks associated with each...
7274213 Method and apparatus for automatic protocol generation  
A dedicated protocol generation unit provides the ability to detect validity of data received from a configurable logic block, such as a programmable logic device (PLD). Data valid signaling is...
7274211 Structures and methods for implementing ternary adders/subtractors in programmable logic devices  
Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder...
7271617 Electronic circuit with array of programmable logic cells  
An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode....
7268584 Adder circuitry for a programmable logic device  
A PLD having logic blocks capable of performing addition with a constant and non-constant value where the constant value is provided directly to an adder, without first passing it through a look up...
7265579 Field programmable gate array incorporating dedicated memory stacks  
A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and...
7265577 Integrated circuits with RAM and ROM fabrication options  
The present invention relates to electronic integrated circuits (ICs) that retain identical functionality with better performance or lower power dissipation under RAM and hard-wire ROM fabrication...
7265578 In-system programming of non-JTAG device using SPI and JTAG interfaces of FPGA device  
A first programmable device comprises non-dedicated, programmable resources including programmable logic; dedicated circuitry; a Joint Test Action Group (JTAG) interface adapted to selectively...
7263456 On circuit finalization of configuration data in a reconfigurable circuit  
Reconfigurable circuits with configuration data loaders are described herein. The configuration data loaders are adapted to enable on circuit finalization of configuration data provided in symbolic...
7256612 Programmable logic block providing carry chain with programmable initialization values  
A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block...
7253657 Apparatus and methods for configuration of programmable logic devices  
A programmable logic device (PLD) includes configuration circuitry. The configuration circuitry is adapted to receive serial configuration data from a configuration device. The configuration...
7245147 Interface for a programmable logic device  
The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core...
7242217 Output reporting techniques for hard intellectual property blocks  
Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal,...
7242218 Techniques for combining volatile and non-volatile programmable logic on an integrated circuit  
Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is...
7239173 Programmable memory element with power save mode in a programmable logic device  
A memory element structure in a programmable logic device (PLD) reduces power consumption by placing the memory element in a power save mode when the memory element is unused in a user design...
7237106 System for loading configuration data into a configuration word register by independently loading a plurality of configuration blocks through a plurality of configuration inputs  
A programmable device with an improved system for loading configuration data compresses configuration data by composing configuration data out of pairs of control words and data words. The...
7236009 Operational time extension  
Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The...
7233168 Methods of setting and resetting lookup table memory cells  
Methods of setting and/or resetting a lookup table (LUT) programmable to operate in shift register mode. The LUT is configured to operate as a shift register, and the final bit of the shift...
7227379 Nanoscale latch-array processing engines  
One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a...
7218142 Switch matrix circuit, logical operation circuit, and switch circuit  
A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G 1 of a transistor M 1 in a switch cell SC is connected...
7218143 Integrated circuit having fast interconnect paths between memory elements and carry logic  
A programmable logic block provides fast interconnect paths between memory element output terminals and the input terminals of carry multiplexers in the same logic block. An integrated circuit...
7218139 Programmable integrated circuit providing efficient implementations of arithmetic functions  
Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output...
7218141 Techniques for implementing hardwired decoders in differential input circuits  
Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential...
7212448 Method and apparatus for multiple context and high reliability operation of programmable logic devices  
A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting...
7196541 Electronic circuit with array of programmable logic cells  
An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode....
7196942 Configuration memory structure  
A configuration memory structure includes one or more distributed buffers cascaded together, the output of a first buffer driving an output data line and complementary output data line which...
7193437 Architecture for a connection block in reconfigurable gate arrays  
An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic...
7193436 Fast processing path using field programmable gate array logic units  
The described embodiments relate to the general area of Field Programmable Gate Arrays (FPGAs), and, in particular, to the architecture and the structure of the building blocks of the FPGAs....
7190190 Programmable logic device with on-chip nonvolatile user memory  
A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a...
RE39510 FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections  
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is...
7183796 Configuration memory implementation for LUT-based reconfigurable logic architectures  
A reconfigurable processing unit ( 1 ) is described which comprises, data flow controlling elements ( 10 ), data manipulating elements ( 20 ), a configuration memory unit ( 30 ) comprising a...
7183801 Programmable logic auto write-back  
A first configuration controller loads configuration data into a programmable logic device. The first controller is coupled with a first configuration memory and manages couplings of the memory to...
7180328 Apparatus and method for large hardware finite state machine with embedded equivalence classes  
A programmable finite state machine (FSM) includes, in part, a first address calculation logic block, a first lookup table, a second address calculation logic block, and a second lookup table. The...
7180813 Programmable system device having a shared power supply voltage generator for FLASH and PLD modules  
A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of...
7176715 Computer combinatorial multipliers in programmable logic devices  
Disclosed is a device and method for configuring a register in a PLD to operate as a logical AND gate. So configuring a register allows it to be used in a multiplication carried out by the PLD. A...
7173840 Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register  
In order to program a memory module, some of its inputs are stimulated via internal memory locations of a so-called boundary scan (BSCAN) register that is provided in the form of an IC or ASIC. In...
7170316 Programmable logic array latch  
A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic...
Matches 101 - 150 out of 668 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 >