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6005411 Monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type  
The present invention is a monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type, which cells allow the signal...
5999015 Logic region resources for programmable logic devices  
A programmable logic device has subregions of programmable logic grouped together in logic regions. The subregions in each region share several control signals, which can be selected either from...
5990702 Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits  
A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides routing of signals between the...
5986467 Time-multiplexed programmable logic devices  
Described are a method and circuit for time-multiplexing two or more PLDS. The invention allows a pair of PLDs to sequentially perform more than two logic functions. The PLDs share common input and...
5977792 Configurable logic circuit and method  
Configurable logic circuit (10,110) and method may comprise a control circuit (12,112) and a logic circuit (14,114). The control circuit (12,112) may generate an intermediate clock function...
5969539 Product term exporting mechanism and method improvement in an EPLD having high speed product term allocation structure  
An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for simultaneous product term exporting to both previous and...
5959467 High speed dynamic differential logic circuit employing capacitance matching devices  
The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input...
5945841 Block segmentation of configuration lines for fault tolerant programmable logic device  
A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to...
5933023 FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines  
A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and...
5926036 Programmable logic array circuits comprising look up table implementation of fast carry adders and counters  
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the...
5917337 Programmable I/O cell with data conversion capability  
A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components...
5914616 FPGA repeatable interconnect structure with hierarchical interconnect lines  
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length...
5900742 Interface cell for a programmable integrated circuit employing antifuses  
An interface cell for a programmable integrated circuit includes a pad, an input buffer, a first routing conductor, a plurality of second routing conductors, and a plurality of antifuses. The input...
5898317 Configurable monolithic semiconductor circuit and method for configuring  
A ferroelectric memory array (20) monolithically integrated with a field programmable gate array (32) into a semiconductor circuit (10). The ferroelectric memory array (20) is suitable for a...
5889413 Lookup tables which double as shift registers  
A logic element for an FPGA which can be configured as any one of a random access memory, a shift register and a lookup table. The logic element includes a plurality of memory cells which are...
5886538 Composable memory array for a programmable logic device and method implementing same  
A composable memory array for a programmable logic device includes a plurality of dedicated, serially coupled memory tiles. Each memory tile includes a plurality of dual-port memory cells, each...
5886537 Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells  
A parallel processing system composed of a regular array of programmable logic devices, each of which can be configured to perform any logical mapping from inputs to outputs. The configuration of...
5883524 Low overhead memory designs for IC terminals  
An integrated circuit includes a terminal which is accessible externally of the integrated circuit, and circuitry (LOB) coupled to said terminal and operable to latch at said terminal a signal...
5883525 FPGA architecture with repeatable titles including routing matrices and logic matrices  
An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix...
5880595 IC having memoried terminals and zero-delay boundary scan  
An electronic integrated circuit includes a signal path for carrying a functional signal between functional logic (15) and an external terminal, which signal path includes a memory element (121,...
5874834 Field programmable gate array with distributed gate-array functionality  
A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic...
5869980 Programming programmable transistor devices using state machines  
An integrated circuit with programmable transistors is programmed via a state machine on the integrated circuit. For example, the integrated circuit may be a programmable logic device, and the...
5859544 Dynamic configurable elements for programmable logic devices  
A programmable logic device using dynamic programmable elements to store configuration data is refreshed by periodic writing of configuration data from the source memory into the dynamic...
5852365 Variable logic circuit and semiconductor integrated circuit using the same  
A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned...
5850151 Programmable logic array intergrated circuit devices  
A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns....
5844422 State saving and restoration in reprogrammable FPGAs  
Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are...
5838165 High performance self modifying on-the-fly alterable logic FPGA, architecture and method  
A technique for configuring arrays of programmable logic cells, including those associated with FPGA devices, through a novel DRAM-based configuration control structure that enables not only...
5835998 Logic cell for programmable logic devices  
A programmable logic array integrated circuit has a plurality of regions of programmable logic. Each region includes a plurality of logic modules, each of which is programmable to perform any of...
5831448 Function unit for fine-gained FPGA  
An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of...
5821772 Programmable address decoder for programmable logic device  
For an FPGA having a configuration memory arranged in rows and columns, a programmable address decoder with a counter selects the order in which columns of memory cells will be programmed and...
5811986 Flexible synchronous/asynchronous cell structure for a high density programmable logic device  
A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell...
5811985 Output multiplexer circuit for input/output block  
A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a...
5804986 Memory in a programmable logic device  
A programmable logic device includes a plurality of logic blocks coupled to an interconnect matrix, wherein one of the plurality of logic blocks comprises configurable memory logic having control...
5804987 LSI chip having programmable buffer circuit  
An LSI chip is mounted on an LSI board. Sub-buffer circuit areas where input buffers, output buffers or input/output buffers are to be formed are provided in signal lines extending from the pad to...
5801547 Embedded memory for field programmable gate array  
A programmable logic device has a configuration memory which is partitioned so that it includes at least one subarray available through the programmable interconnect of the user configurable logic...
5781032 Programmable inverter circuit used in a programmable logic cell  
A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals,...
5764078 Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix  
Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of...
5764076 Circuit for partially reprogramming an operational programmable logic device  
A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used...
5760603 High speed PLD "AND" array with separate nonvolatile memory  
The invention is a unique high speed Programmable Logic Device ("PLD") AND array with separate nonvolatile memory. The invention utilizes a separate nonvolatile memory to isolate the effect of...
5760611 Function generator for programmable gate array  
A programmable logic circuit provides a variety of logic functions including AND/NAND, OR/NOR, XOR/XNOR. Selection of logic function is provided by controlling inputs, using programmable inverters...
5760602 Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA  
A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are...
5761483 Optimizing and operating a time multiplexed programmable logic device  
A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the...
RE35797 Logic array having high frequency internal clocking  
A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked...
5748012 Methodology to test pulsed logic circuits in pseudo-static mode  
A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test...
5744980 Flexible, high-performance static RAM architecture for field-programmable gate arrays  
A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors...
5742180 Dynamically programmable gate array with multiple contexts  
An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable...
5714890 Programmable logic device with fixed and programmable memory  
An improved programmable logic device (PLD) comprises a programmable AND first array to which a set of PLD input lines are selectively connectable and providing a set of outputs which are...
5703498 Programmable array clock/reset resource  
A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals...
5694056 Fast pipeline frame full detector  
A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer...
5687325 Application specific field programmable gate array  
An application specific field programmable gate array ("ASFPGA") includes at least two fixed functional units in a single IC chip. Depending upon a specific application for the ASFPGA, the fixed...
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