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6819135 Fast signal conductor networks for programmable logic devices  
A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A...
6816562 Silicon object array with unidirectional segmented bus architecture  
A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus...
6815981 Programmable logic array integrated circuit devices  
A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns....
RE38651 Variable depth and width memory device  
A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address...
6812737 Programmable logic circuit device having look up table enabling to reduce implementation area  
A programmable logic circuit device has a plurality of logic blocks, a plurality of routing wires, a plurality of switch circuits, a plurality of connection blocks, and an I/O block performing an...
6812738 Vector routing in a programmable logic device  
A PLD is disclosed that uses vector routing between components. A vector routing path is coupled between the components and includes a group of wires for routing a group of bits as one vector so...
6806732 FPGA with improved structure for implementing large multiplexers  
Novel structures for implementing wide multiplexers from user designs in FPGA CLBs. Input multiplexers providing the function generator data input signals are modified to function not just based on...
6798239 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry  
Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions...
6798242 Programmable logic device with hierarchical interconnection resources  
A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal...
6788104 Field programmable logic device with efficient memory utilization  
A field programmable logic device includes at least two independently configurable embedded memory structures. The memory structures may differ in at least one parameter, such as memory size,...
6777979 FIFO memory architecture  
A FIFO coordinates with registers of a programmable semiconductor device, wherein the registers are clocked according to an internal clock and words are written into the FIFO according to a write...
6774672 Field-programmable gate array architecture  
A field-programmable gate array (FPGA) is disclosed. A two-by-two array of FPGA tiles is surrounded by a JTAG interface, a Configuration interface and a BIST interface. Each interface is located...
6774669 Field programmable gate array freeway architecture  
The disclosed system relates to a freeway routing system and a fast-freeway routing system for a field programmable gate array. The field programmable gate array comprises a two by two array of...
6774670 Intra-tile buffer system for a field programmable gate array  
The invention relates to an intra-tile buffering system for a field programmable gate array. The field programmable gate array comprises a field programmable gate array tile comprising a number of...
6768338 PLD lookup table including transistors of more than one oxide thickness  
A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The...
6754881 Field programmable network processor and method for customizing a network processor  
A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of...
6748368 Proprietary core permission structure and method  
A programmable logic device includes a non-volatile permission memory block to enable a customer to utilize a proprietary core. In one embodiment, the core supplier designs its core to check for a...
6748456 PLD configuration port architecture and logic  
A programmable logic device (PLD) comprising a configuration controller. The configuration controller may be configured to (i) retrieve data and (ii) program a number of configuration bits of the...
6747479 Interface scheme for connecting a fixed circuitry block to a programmable logic core  
An apparatus comprising one or more configurable interface tiles. The configurable interface tiles may be configured to communicate one or more signals between one or more programmable logic cores...
6747478 Field programmable gate array with convertibility to application specific integrated circuit  
A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed...
6745317 Three level direct communication connections between neighboring multiple context processing elements  
A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a...
6744278 Tileable field-programmable gate array architecture  
An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing...
6744274 Programmable logic core adapter  
A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an...
6731133 Routing structures for a tileable field-programmable gate array architecture  
A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of...
6725441 Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices  
A method and apparatus for generating a configuration bitstream for a programmable logic device using logic ports associated with logic cores. Logic ports are associated with respective ones of a...
6714041 Programming on-the-fly (OTF)  
A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data...
6714044 Hi-speed parallel configuration of programmable logic  
Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (...
6714043 Output buffer having programmable drive current and output voltage limits  
An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL,...
6708190 Reduced product term carry chain  
A programmable logic device comprising one or more macrocells and a product term array. The macrocells may comprise logic that may be configured to (i) generate and propagate a carry signal and...
6708191 Configurable logic block with and gate for efficient multiplication in FPGAS  
An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function...
6707314 Integrated circuit device, electronic equipment, and method of placement of an integrated circuit device  
A macrocell MC 1 including a physical-layer circuit in accordance with USB 2.0 or the like is placed at a corner of an integrated circuit device ICD. Data terminals DP and DM are placed in an I/O...
6703860 I/O block for a programmable interconnect circuit  
A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may programmably...
RE38451 Universal logic module with arithmetic capabilities  
A universal logic module for use in a programmable logic device, capable of generating all logical functions of three variables or less. The universal logic module also implements a full adder with...
6696855 Symmetric logic block input/output scheme  
A programmable logic device includes a plurality of clusters of logic elements. Each of the clusters may include a respective programmable interconnect matrix with each of the logic blocks of each...
6696856 Function block architecture with variable drive strengths  
Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The...
6693454 Distributed RAM in a logic array  
Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of...
6693452 Floor planning for programmable gate array having embedded fixed logic circuitry  
Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions...
6693453 Re-programmable logic array  
A re-programmable logic array includes at least one input and at least one output. An input capacitive device is coupled to the at least one input. Internal gating devices are coupled to the input...
6686767 Apparatus and method for controlling a three-state bus  
A signal control circuit includes a set of signal lines that form a data bus. A set of three-state driver columns is connected to the data bus; each three-state driver column is connected to each...
6670826 Configurable logic block with a storage element clocked by a write strobe pulse  
A configurable logic block for a programmable logic device includes a storage element having a latch clocked by a write strobe pulse. The storage element uses a write strobe signal and, optionally,...
6670825 Efficient arrangement of interconnection resources on programmable logic devices  
Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be...
6670824 Integrated polysilicon fuse and diode  
An integrated polysilicon fuse and diode and methods of making the same are provided. The integrated polysilicon fuse and diode combination may be implemented in a programmable cross point fuse...
6668237 Run-time reconfigurable testing of programmable logic devices  
Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time...
6664807 Repeater for buffering a signal on a long data line of a programmable logic device  
A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset...
6657456 Programmable logic with on-chip DLL or PLL to distribute clock  
A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit...
6653861 Multi-level routing structure for a programmable interconnect circuit  
A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may have a partially...
6654944 Two-dimensional C-element array  
Embodiments of the present invention include a two-dimensional C-element array that may be configured to propagate a periodic waveform. The two-dimensional C-element array is advantageous in...
6650143 Field programmable gate array based upon transistor gate oxide breakdown  
A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and...
6637017 Real time programmable feature control for programmable logic devices  
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more input signals. The second circuit may...
6631510 Automatic generation of programmable logic device architectures  
The invention consists of a new component called the Architecture Generation Engine added to the CAD system for implementing circuits into PLD architectures and for evaluating performances of...
Matches 351 - 400 out of 1113 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >