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7095247 Configuring FPGAs and the like using one or more serial memory devices  
The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration...
7091745 Indicating completion of configuration for programmable devices  
Various approaches for indicating completion of configuration of programmable logic devices are disclosed. In one embodiment, a plurality of configuration memory cells are arranged for storage of a...
7088133 Programmable logic device with high speed serial interface circuitry  
A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that...
7088132 Configuring FPGAs and the like using one or more serial memory devices  
The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration...
7088134 Programmable logic device with flexible memory allocation and routing  
A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into...
7086025 Programmable logic device partitioning method for application specific integrated circuit prototyping  
The interconnect pin count between field programmable gate arrays (FPGAS) used in prototyping an application specific integrated circuit (ASIC) is reduced without compromising the prototyping by...
7084664 Integrated circuits with reduced interconnect overhead  
Integrated circuits are provided that use on-chip data compression and decompression to minimize consumption of interconnect resources. Parallel-to-serial converter circuitry can use time-division...
7078932 Programmable logic device with reduced power consumption  
The present invention provides a programmable logic device with reduced power consumption comprising, a first set of data storage elements, at least a first power supply connected to the said first...
7080226 Field programmable gate array (FPGA) configuration data path for module communication  
Data is transferred on a field programmable gate array (FPGA) by (1) retrieving a first set of data from a first block RAM column of a configuration memory of the FPGA, (2) storing the first set of...
7075331 Methods and systems for providing hardware assisted programming of a programmable logic device in an embedded system  
A programmable logic device (PLD) in a microprocessor system is programmed with minimal load on system resources. A microprocessor reads programming data from a first memory using a parallel bussed...
7075333 Programmable circuit optionally configurable as a lookup table or a wide multiplexer  
Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is...
7075332 Six-input look-up table and associated memory control circuitry for use in a field programmable gate array  
A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. Sixty-four write control circuits are coupled to the 64 memory cells. A first write address decoder...
7071732 Scalable complex programmable logic device with segmented interconnect resources  
A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and...
7071726 Selectable dynamic reconfiguration of programmable embedded IP  
Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the...
7068068 Re-configurable mixed-mode integrated circuit architecture  
An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured...
7068071 Integrated circuit with overclocked dedicated logic circuitry  
An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal...
7068069 Control circuit and reconfigurable logic block  
A control circuit for providing a control signal to build a logic circuit includes a latch circuit including first and second inverted logic gates; a first variable resistive memory provided...
7064580 Mask-programmable logic device with programmable portions  
A mask-programmable logic device includes some circuitry that is electrically programmable as in conventional programmable logic devices. This allows a user to adjust certain characteristics of...
7064577 Method and apparatus for supporting variable speed configuration hardware  
A programmable logic device (PLD) includes a plurality of programmable resources. The PLD includes configuration hardware that configures a first programmable resource at a first rate and a second...
7064579 Alterable application specific integrated circuit (ASIC)  
A highly economical alterable ASIC contains multiple fully optimized custom ASIC designs in one IC foot-print, each design utilizing the entire IC. The user can switch between multiple...
7065732 Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane  
A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is...
7061269 I/O buffer architecture for programmable devices  
Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect...
7062586 Method and apparatus for communication within a programmable logic device using serial transceivers  
Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module....
7061268 Initializing a carry chain in a programmable logic device  
A logic circuit includes a first series of logic elements. Each logic element has a look-up table (LUT) and a dedicated adder to implement an arithmetic mode in the logic element. The logic circuit...
7061271 Six-input look-up table for use in a field programmable gate array  
A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. A set of 64 transmission gates is configured to receive the 64 four data values. A first input signal...
7057413 Large crossbar switch implemented in FPGA  
A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch,...
7058920 Methods for designing PLD architectures for flexible placement of IP function blocks  
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
7054967 SRAM bus architecture and interconnect to an FPGA  
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of...
7053654 PLD lookup table including transistors of more than one oxide thickness  
A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The...
7046034 Programmable logic device having heterogeneous programmable logic blocks  
A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry...
7047166 Method and VLSI circuits allowing to change dynamically the logical behavior  
A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The...
7043611 Reconfigurable memory controller  
A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a...
7038489 Method for sharing configuration data for high logic density on chip  
A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is...
7038952 Block RAM with embedded FIFO buffer  
A programmable logic device includes a block random access memory (“BRAM”) with an embedded first in, first out (“FIFO”) controller. Embedding the FIFO logic in silicon, rather than...
7038488 Programmable logic device with transceiver and reconfigurable PLL  
A programmable logic device (PLD) includes a transceiver, configurable phase-locked loop (PLL) circuits, and programmable logic circuits. The logic circuits and PLL circuits are programmed to...
7030650 Fracturable incomplete look up table area efficient logic elements  
Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and,...
7023239 Automated boundary-scan chain composition method using a device database and access mechanism for storing and retrieving situation-dependent operation options  
A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically...
7019558 Conversion of configuration data to match communication protocol  
Various approaches for converting configuration data for programmable circuits are disclosed. In one embodiment, a first configuration bitstream is provided. The first configuration bitstream has a...
7020764 Semiconductor processing device  
A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit...
7010772 Method and apparatus for generating superset pinout for devices with high-speed transceiver channels  
A method for generating a superset pinout for a family of devices. First, a pinlist is defined for each device within the family of devices. Second, a superset listing of pins is generated from the...
7009419 Method and apparatus for selecting an encryption integrated circuit operating mode  
A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically...
7009421 Field programmable gate array core cell with efficient logic packing  
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA...
7010667 Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity  
An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system...
7003660 Pipeline configuration unit protocols and communication  
An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular...
7002369 Implementing complex clock designs in field programmable devices  
An aspect of the present invention simplifies the implementation of complex clock designs in field programmable devices (FPD). To implement a circuit logic containing base sequential elements...
7002370 Multiplexer configuration for programmable logic device  
A multiplexer is configured on a programmable logic device using a plurality of four-input look-up tables chained together. The required number of look-up tables is about one-half the number of...
7000212 Hierarchical general interconnect architecture for high density FPGA'S  
Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a hierarchical general interconnect architecture in which: (1) reliance on single-length general...
6998872 Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs  
Lookup table (LUT) circuits can optionally be configured as two or more smaller LUTs having independent input signals. A LUT circuit includes a tristate buffer circuit coupled between first and...
6999952 Linear associative memory-based hardware architecture for fault tolerant ASIC/FPGA work-around  
A programmable logic unit (e.g., an ASIC or FPGA) having a feedforward linear associative memory (LAM) neural network checking circuit which classifies input vectors to a faulty hardware block as...
6992503 Programmable devices with convertibility to customizable devices  
A semiconductor device with two selectable manufacturing configurations, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially...
Matches 251 - 300 out of 1113 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >