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5982193 Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits  
A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides routing of signals between the...
5969543 Input signal interface with independently controllable pull-up and pull-down circuitry  
An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down...
5968196 Configuration control in a programmable logic device using non-volatile elements  
A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG...
5969539 Product term exporting mechanism and method improvement in an EPLD having high speed product term allocation structure  
An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for simultaneous product term exporting to both previous and...
5963050 Configurable logic element with fast feedback paths  
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an...
5963048 Method for programming complex PLD having more than one function block type  
A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block...
5959465 Fast Nor-Nor PLA operating from a single-phase clock  
A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming...
5959467 High speed dynamic differential logic circuit employing capacitance matching devices  
The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input...
5955892 Programmable integrated circuit having test antifuse circuitry for testing programming conductors  
In a programmable integrated circuit such as a field programmable gate array (see FIG. 6), a programming driver is coupled to one end of a programming conductor and a test transistor/test antifuse...
5952852 Fast wide decode in an FPGA using probe circuit  
In a first aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a test probe circuit associated with a column in the array, selecting at...
5952846 Method for reducing switching noise in a programmable logic device  
A method for programming PLDs in which feedback signals are alternately programmed to produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by...
5953537 Method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device  
A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be...
5941974 Serial interface with register selection which uses clock counting, chip select pulsing, and no address bits  
A method and apparatus for providing serially shifted data to a plurality of registers (51 through 56) begins by providing an enable signal (14). A first time portion of the enable signal (14) is...
5942913 FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines  
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. The interconnect structure includes both buffered and unbuffered interconnect lines. Some...
5942914 PLD with split multiplexed inputs from global conductors  
An improved multiplexer arrangement for connecting global conductors to logic array block (LAB) inputs. A single connection connects a particular global conductor to an input path to LABs on both...
5936425 Tri-statable input/output circuitry for programmable logic  
Each output signal of programmable logic circuitry is made programmably available to drive one or more of a plurality of tri-statable input/output pins of the circuitry. Each output signal is also...
5936424 High speed bus with tree structure for selecting bus driver  
According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of...
5926036 Programmable logic array circuits comprising look up table implementation of fast carry adders and counters  
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the...
5920882 Programmable circuit assembly and methods for high bandwidth data processing  
A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory...
5914616 FPGA repeatable interconnect structure with hierarchical interconnect lines  
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length...
5915123 Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements  
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to...
5910733 Method and system for layout and schematic generation for heterogeneous arrays  
A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types....
5907248 FPGA interconnect structure with high-speed high fanout capability  
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length...
5905385 Memory bits used to couple look up table inputs to facilitate increased availability to routing resources particularly for variable sized look up tables for a field programmable gate array (FPGA)  
A field programmable gate array (FPGA) with pass gates included in configurable logic block (CLB) circuitry to enable look up tables (LUT) inputs to be selectively tied together when a larger LUT...
5903165 Programmable logic array with a hierarchical routing resource  
A configurable semi-conductor integrated circuit has an area thereof formed with a plurality of logic circuits at discrete sites or cells respectively defining a matrix array of cells. The matrix...
5901279 Connection of spares between multiple programmable devices  
A method of coupling logic devices using spares. A first logic device is coupled to a second logic device using a first plurality of spares. The first logic device is coupled to a third logic...
5898317 Configurable monolithic semiconductor circuit and method for configuring  
A ferroelectric memory array (20) monolithically integrated with a field programmable gate array (32) into a semiconductor circuit (10). The ferroelectric memory array (20) is suitable for a...
5898318 Programmable logic array integrated circuits with enhanced cascade  
A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A global interconnect structure...
5892370 Clock network for field programmable gate array  
A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to...
5892961 Field programmable gate array having programming instructions in the configuration bitstream  
A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming...
5889412 Condensed single block PLA plus PAL architecture  
A condensed single block PAL plus PLA architecture utilizing a rectangular shape is shown. By interleaving the ORterms of the PLA array with the Pterms of the PAL array, a significant amount of die...
5889411 FPGA having logic element carry chains capable of generating wide XOR functions  
An aspect of the invention provides an FPGA interconnect and logic block structure preferably included in an array of identical tiles. By allowing the complement of a carry multiplexer input signal...
5886537 Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells  
A parallel processing system composed of a regular array of programmable logic devices, each of which can be configured to perform any logical mapping from inputs to outputs. The configuration of...
5883526 Hierarchical interconnect for programmable logic devices  
A hierarchical interconnect structure between logic elements, logic array blocks and global interconnects in a programmable logic device is disclosed. The present invention provides a first group...
5883525 FPGA architecture with repeatable titles including routing matrices and logic matrices  
An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix...
5880598 Tile-based modular routing resources for high density programmable logic device  
Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate...
5874834 Field programmable gate array with distributed gate-array functionality  
A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic...
5872462 Programmable logic array and method for its design using a three step approach  
A PLA whose slowest product terms are located as close as possible to the true/complement generators or input buffers. The associated input buffers and product terms are partitioned into two or...
5872463 Routing in programmable logic devices using shared distributed programmable logic connectors  
The output signals of the logic regions in a programmable logic integrated circuit device are programmably connectable to output bus conductors. Each such output signal can be applied to any of...
5869981 High density programmable logic device  
Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of...
5867037 Method and apparatus of programming FPGA devices through ASIC devices  
A method and apparatus for receiving and transmitting programming data through an application specific integrated circuit is provided. In a first embodiment, the application specific integrated...
5861761 Hierarchically connectable configurable cellular array  
An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of...
5850151 Programmable logic array intergrated circuit devices  
A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns....
5847578 Programmable multiplexing input/output port  
A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a...
5847579 Programmable logic array with improved interconnect structure  
A programmable logic array improves connectivity and more efficiently routes signals between logic blocks by allowing programmable connections between each logic block and the horizontal...
5848285 Macrocell having a dual purpose input register for use in a logic device  
The macrocell is configured to allow a single register to be employed either as a register for storing internal macrocell product terms (or logical combinatorial thereof) or as an input register...
5847580 High speed bidirectional bus with multiplexers  
A multiplexer chain is coupled to two logic gates which in turn propagate their respective output signals in different directions, thereby providing bidirectional signal distribution. The output...
5841295 Hybrid programmable logic device  
A programmable monolithic integrated logic circuit that includes look up table circuits and programmable logic array-like circuits. The integrated circuit can include a first number of the look up...
5841867 On-chip programming verification system for PLDs  
The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention...
5838167 Method and structure for loading data into several IC devices  
An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred...
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