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6081914 Method for implementing priority encoders using FPGA carry logic  
The invention provides a method for implementing an HDL-specified priority encoder as carry logic in an FPGA. A first embodiment of the method includes the steps of: 1) detecting an priority...
6069488 Programmable logic device with versatile exclusive or architecture  
A programmable logic device (PLD) includes a fixed EXCLUSIVE OR gate and a programmable logic array (PLA). The PLA includes a plurality of AND gate and a plurality of OR gates, the output of each...
6069489 FPGA having fast configuration memory data readback  
An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by...
6069490 Routing architecture using a direct connect routing mesh  
A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a...
6066960 Programmable logic device having combinational logic at inputs to logic elements within logic array blocks  
AND gates are used at the inputs to logic elements in a programmable logic device. This allows more efficient configuration of the logic elements for basic functions such as a multiplier, clearable...
6066959 Logic array having multi-level logic planes  
A logic array includes an AND plane, a first OR plane, and a second OR plane. The AND plane is adapted to receive a plurality of logic array inputs and provide a plurality of minterms. Each minterm...
6066961 Individually accessible macrocell  
A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line include a programmable logic device (PLD) array, at least one input pin, at least two...
6064225 Global signal distribution with reduced routing tracks in an FPGA  
The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as...
6060903 Programmable logic device architecture incorporating a dedicated cross-bar switch  
A programmable logic device architecture incorporating a cross-bar switch is disclosed. In a preferred embodiment, a plurality of logic cells is programmably interconnected to form an array of...
6057703 Reconfigurable programmable logic devices  
Methods and apparatus to reconfigure a programmable logic device on a chip. The device includes a number of configurable elements. The methods include the steps of retrieving reconfiguration data...
6057708 Field programmable gate array having a dedicated internal bus system  
A user-defined logic device, such as a field programmable gate array (FPGA), having a dedicated internal bus, a plurality of dedicated bus interface circuits, and a programmable logic array. The...
6057706 Field programmable gate array with integrated debugging facilities  
A number of enhanced logic elements (LEs) are provided to form a FPGA. Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having...
6054871 Method for self-reconfiguration of logic in a field programmable gate array  
A method for controlling the operation of an FPGA. Initially, a function generator of the FPGA is configured as a ROM look up table which holds a first set of data values. These data values are...
6054873 Interconnect structure between heterogeneous core regions in a programmable array  
A programmable interconnect structure is provided whereby core regions of an integrated circuit having circuits of different functional types therein are connected. Ports are defined in a first...
6055594 Byte accessible memory interface using reduced memory control pin count  
A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for...
6049222 Configuring an FPGA using embedded memory  
An FPGA includes an embedded non-volatile memory coupled to a configuration access port. The configuration access port allows the non-volatile memory to program the configuration memory of the...
6049225 Input/output interface circuitry for programmable logic array integrated circuit devices  
In a programmable logic array integrated circuit device, various techniques are used to increase the flexibility with which the core logic of the device can be connected to the input and/or output...
6043676 Wide exclusive or and wide-input and for PLDS  
A programmable logic device (10) has a number of programmable logic elements (LES) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). An LAB incorporates one or more...
6044417 System for controlling operational characteristics of buffer group where capture registers receive control signals in parallel and update registers transfer control signals to buffer group  
In one aspect of the present invention, a bus buffer is provided. The bus buffer includes at least one buffer group having first and second groups of control input terminals. The first and second...
6037801 Method and apparatus for clocking a sequential logic circuit  
A sequential logic circuit having a series of data signal bistable elements is described. Each data signal bistable element is clocked by a corresponding qualified clock. The qualified clocks are...
6034539 Bonding-option architecture for integrated circuitry  
A bonding-option architecture is provided for use on an IC package for bonding option selections. The bonding-option architecture includes an option pad and a plurality of bonding entries connected...
6034545 Macrocell for data processing circuit  
The present invention provides a macrocell for a data processing circuit, comprising macrocell logic, and an interface for connecting the macrocell logic to a bus of the data processing circuit....
6034542 Bus structure for modularized chip with FPGA modules  
An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance...
6034544 Programmable input/output block (IOB) in FPGA integrated circuits  
A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs) An inter-connect network provides routing of signals between the...
6034541 In-system programmable interconnect circuit  
A programmable interconnect circuit includes multiple input/output cells, each corresponding to an input/output pin, and a global routing resource for routing signals received at the input pins to...
6034543 Programmable logic array structure having reduced parasitic loading  
The present invention provides a PLA structure having logic interposed between an AND plane and an OR plane, wherein the interposed logic provides an additional set of minterms to the OR plane such...
6031982 Layout design of integrated circuit, especially datapath circuitry, using function cells formed with fixed basic cell and configurable interconnect networks  
A group of function cells (e.g., 40), each created from one or more implementations of a fixed basic cell (20), are utilized in designing a layout for at least part of an integrated circuit. Each...
6028447 FPGA having predictable open-drain drive mode  
A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal...
6028446 Flexible synchronous and asynchronous circuits for a very high density programmable logic device  
A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell...
6028445 Decoder structure and method for FPGA configuration  
A method is provided for configuring an FPGA using a decoder implemented in the FPGA. Specifically, an external configuration device or an embedded non-volatile memory configures a first portion of...
6029236 Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM  
A field programmable gate array (FPGA) comprising a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a...
6025736 Fast reprogrammable logic with active links between cells  
A high speed active link switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high...
6023570 Sequential and simultaneous manufacturing programming of multiple in-system programmable systems through a data network  
An in-system programmable (ISP) system, having a plurality of ISP devices, can be programmed by remote access from a host controller. The remote access can be accomplished over a wired data...
6020757 Slew rate selection circuit for a programmable device  
A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each...
6020756 Multiplexer enhanced configurable logic block  
A configurable logic block (CLB) which includes a function generator, carry logic and a first multiplexer. To operate the CLB as a multiplier, the function generator and the carry logic are each...
6020755 Hybrid programmable gate arrays  
A single integrated circuit (IC) having one or more regions of mask-programmed device (MPD) logic for implementing permanent functions and one or more regions of field-programmable gate-array...
6018787 System for generating chip select signals based on coded and uncoded address signals  
A chip selection enable apparatus which outputs one of plural chip enable signals in correspondence to which of plural address signals appear on an address bus. The chip selection apparatus...
6018251 Programmable integrated circuit having parallel routing conductors coupled to programming drivers in different locations  
A programmable integrated circuit (see FIG. 18) includes a plurality of interface cells with programmable antifuses disposed on a branch of a routing conductor. The routing conductor extends in a...
6016063 Method and apparatus for connecting long lines to form wide logic functions  
The present invention provides a method and apparatus for combining tristate buffers into wide logic functions. The invention provides for an arbitrary number of drivers to be accommodated on a...
6008666 Variable-delay interconnect structure for a programmable logic device  
Described is a user-controlled, variable-delay interconnect structure for a programmable logic device (PLD), and a method for using this structure. In accordance with the invention, the signal...
RE36443 Dialer with internal option select circuit programmed with externally hardwired address  
An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The...
6002991 Method and apparatus for measuring localized voltages on programmable integrated circuits  
A method is described for measuring localized operating temperatures and voltages on an integrated circuit. The integrated circuit includes an oscillator circuit with a frequency that varies with...
6002268 FPGA with conductors segmented by active repeaters  
An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output...
5999015 Logic region resources for programmable logic devices  
A programmable logic device has subregions of programmable logic grouped together in logic regions. The subregions in each region share several control signals, which can be selected either from...
5999014 Method for concurrently programming or accessing a plurality of in-system-programmable logic devices  
An improved method for concurrently programming in-system programmable logic devices (PLDs). More specifically, where within a plurality of serially connected PLDs, there are devices having...
5999016 Architectures for programmable logic devices  
A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each...
5986467 Time-multiplexed programmable logic devices  
Described are a method and circuit for time-multiplexing two or more PLDS. The invention allows a pair of PLDs to sequentially perform more than two logic functions. The PLDs share common input and...
5986469 Programmable integrated circuit having L-shaped programming power buses that extend along sides of the integrated circuit  
A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each...
5982195 Programmable logic device architectures  
A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection...
5982196 Programmable logic device producing a complementary bit line signal  
A programmable logic device includes a plurality of logic elements. Each logic element includes a raw of transistors formed between a bit line and a source line, elements for generating a...
Matches 651 - 700 out of 1113 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >