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6172520 FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA  
The present invention allows one portion of an FPGA to reconfigure another portion of the same FPGA. The invention makes use of input/output ports that can be connected on the input side to a frame...
6169418 Efficient routing from multiple sources to embedded DRAM and other large circuit blocks  
An improved routing system and method allow routing of pluralities of signals to circuit blocks on integrated circuit chips using minimal die area. The improved routing system employs a plurality...
6166559 Redundancy circuitry for logic circuits  
Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the...
6163167 Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area  
A method for generating a two-turn programmable routing structure is provided for a programmable logic device that provides a high degree of routing flexibility, with lane-changing capability,...
6163168 Efficient interconnect network for use in FPGA device having variable grain architecture  
A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the...
6163166 Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers  
A programmable logic device has buffers that may be selectively programmed for Schmitt-triggered and threshold-triggered operation. The programmable Schmitt-triggered buffers are connected to...
6157207 Protection of logic modules in a field programmable gate array during antifuse programming  
To protect logic module output devices from high voltages, logic modules are not powered during antifuse programming. In some embodiments, two separate power input terminals VCC1 and VCC2 are...
6157209 Loadable up-down counter with asynchronous reset  
In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal...
6157212 Programmable logic device with expandable-width memory regions  
Circuitry is provided that allows programmable memory regions to use the data input and output resources of nearby programmable logic regions. The regular width of the data input port of a...
6154050 Internal tristate bus with arbitration logic  
A programmable logic device having an internal tristate bus is provided. The internal tristate bus may be driven by a plurality of driving elements. Such a tristate bus, and the circuitry for...
6154049 Multiplier fabric for use in field programmable gate arrays  
A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of multiplier tiles. The CLEs can...
6154048 Structure and method for loading narrow frames of data from a wide input bus  
An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by...
6154053 Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch  
A carry logic circuit is provided for an array of configurable logic blocks (CLBs), wherein each configurable logic block includes an array of logic cells arranged in rows and columns. At least one...
6150841 Enhanced macrocell module for high density CPLD architectures  
An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different...
6147509 Semiconductor logical device capable of circuit switching without being influenced by transitional effects  
An FPGA is provided with a plurality of logic circuits and memories. By transmitting logic circuit information to the memories of the logic circuits which are not operating, and switching to the...
6145020 Microcontroller incorporating an enhanced peripheral controller for automatic updating the configuration date of multiple peripherals by using a ferroelectric memory array  
The present invention is an enhanced peripheral controller communicating between a microcontroller and multiple peripherals that increases the speed with which configuration data sets are loaded....
6144220 FPGA Architecture using multiplexers that incorporate a logic gate  
A structure in which blocks of random access memory, or RAM, are integrated with FPGA configurable logic blocks. Routing lines which access configurable logic blocks also access address, data, and...
6140837 Charge pumps of antifuse programming circuitry powered from high voltage compatibility terminal  
A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic...
6140839 Computational field programmable architecture  
A computational field programable architecture targeted for compute intensive applications. The architecture is hierarchical and includes, for implementation of data path circuits, clusters of...
6137307 Structure and method for loading wide frames of data from a narrow input bus  
An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by...
6130551 Synthesis-friendly FPGA architecture with variable length and variable timing interconnect  
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable...
6130550 Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout  
An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output...
6130552 Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution  
A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit...
6127845 Field programmable gate array having internal logic transistors with two different gate insulator thicknesses  
In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second...
6128692 Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices  
A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable...
6125059 Method for erasing nonvolatile memory cells in a field programmable gate array  
In an FPGA, nonvolatile reprogrammable interconnect cells which have a switch transistor and at least one second transistor for programming and sensing, or a second transistor for sensing and a...
6124731 Configurable logic element with ability to evaluate wide logic functions  
The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of...
6122747 Intelligent subsystem interface for modular hardware system  
A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a...
6121823 Electrical circuit for sensors requiring a variety of bias voltages  
An electrical circuit provides a variety of stable and reliable bias voltages to accommodate the bias requirements of various sensor types. The electrical circuit comprises a programmable analog...
6118299 Method and apparatus to generate mask programmable device  
The present invention concerns a mask-programmed cell comprising an input, an output and a transistor. The transistor has a first terminal and a second terminal. The cell may be configured in a...
6118296 Semiconductor integrated logic circuit  
In a semiconductor logic integrated circuit, scan-path-testable flipflop circuits are provided, and scan-path flipflop circuits having a through mode are provided at an input and an output of a...
6118298 Structure for optionally cascading shift registers  
A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift...
6118707 Method of operating a field programmable memory array with a field programmable gate array  
A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among...
6118693 Electrically erasable non-volatile memory cell with integrated SRAM cell to reduce testing time  
In a programmable integrated circuit, by providing a static random access memory (SRAM) cell in each electrically erasable (E 2 ) non-volatile memory cell, testing time of circuits configured by...
6114873 Content addressable memory programmable array  
An array architecture built out of content addressable memories (CAMs) is disclosed. This architecture is re-programmable and exhibits pre-synthesis deterministic timing behavior. This architecture...
6111428 Programmable logic array  
There is provided a programmable logic array in which a precharge circuit is provided separately from precharge transistors. The precharge circuit can connect the one of wirings connecting memory...
6107827 FPGA CLE with two independent carry chains  
The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented...
6107826 Interconnect structure for FPGA with configurable delay locked loop  
A field programmable gate array (FPGA) is provided that includes a plurality of pads and a plurality of delay locked loops (DLLs). Programmable connections enable any one of the DLLs to have...
6104211 System for preventing radiation failures in programmable logic devices  
A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can...
6100714 High density PLD structure with flexible logic built-in blocks  
A programmable logic device (PLD) includes logic built-in blocks (LBB) connected with a programmable interconnection array (PIA). Each LBB has two configurable logic cells sharing a group of...
6101143 SRAM shutdown circuit for FPGA to conserve power when FPGA is not in use  
A circuit and method for FPGAs to allow a user to supply a shutdown signal at an external pin which causes internal circuitry in the FPGA to turn off pass transistors in the word lines of every...
6097210 Multiplexer array with shifted input traces  
An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by...
6097988 Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic  
A logic system is presented including multiple configurable logic blocks (CLBs) implementing a state machine having multiple states, each state being associated with one or more logic functions and...
6094063 Method for level shifting logic signal voltage levels  
The present invention provides an apparatus for converting logic signals of a first voltage level to logic signals of a second voltage level in response to a control signal indicative of whether...
6094065 Integrated circuit with field programmable and application specific logic areas  
A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit...
6094064 Programmable logic device incorporating and input/output overflow bus  
A programmable logic device architecture incorporating a peripheral overflow bus is disclosed. In a preferred embodiment, the programmable logic device has a core region that includes at least a...
6094369 Ferroelectric nonvolatile memory element having capacitors of same dielectric constant and method thereof  
A nonvolatile memory element capable of using desired ferroelectric materials, exhibiting a high reliability and performing processings such as reading of information without destruction of stored...
6091261 Apparatus and method for programmable delays using a boundary-scan chain  
The invention is a system that provides programmable clock delays for logic circuits. The system makes use of the boundary-scan register chain incorporated into logic devices for testing purposes....
6081914 Method for implementing priority encoders using FPGA carry logic  
The invention provides a method for implementing an HDL-specified priority encoder as carry logic in an FPGA. A first embodiment of the method includes the steps of: 1) detecting an priority...
6069488 Programmable logic device with versatile exclusive or architecture  
A programmable logic device (PLD) includes a fixed EXCLUSIVE OR gate and a programmable logic array (PLA). The PLA includes a plurality of AND gate and a plurality of OR gates, the output of each...
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