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7620929 Programmable logic device having a programmable selector circuit  
A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector...
7619442 Versatile bus interface macro for dynamically reconfigurable designs  
Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable...
7619441 Apparatus for interconnecting stacked dice on a programmable integrated circuit  
An apparatus for interconnecting stacked dice on a programmable integrated circuit is described. In one example, an integrated circuit die comprises a programmable integrated circuit that includes...
7616026 System-on-a-chip integrated circuit including dual-function analog and digital inputs  
An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to...
7616025 Programmable logic device adapted to enter a low-power mode  
A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control...
7613943 Programmable system on a chip  
A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a...
7613942 Power mode transition in multi-threshold complementary metal oxide semiconductor (MTCMOS) circuits  
In one embodiment, a method for power mode transition in a multi-threshold complementary metal oxide semiconductor (MTCMOS) circuit includes clustering logic cells in the circuit to a number of...
7612582 Programmable logic controller and related electronic devices  
A programmable device is useful for high speed operation or as a process controller or as a component for implementing PLD or FPGA applications. The programmable device includes programmable logic...
7612581 Apparatus for dynamic deployment of pin functions on a chip  
An apparatus for dynamic deployment of pin functions on a chip is disclosed in the present invention. The apparatus comprises: an input pin receiving unit, capable of integrating a plurality of...
7609089 FPGA architecture at conventional and submicron scales  
Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT...
7609088 Programmable logic array  
A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the...
7609087 Integrated circuit device programming with partial power  
A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the...
7609086 Crossbar control circuit  
A control circuit includes a crossbar array having input columns and output rows configured to store first stored data in the form of high or low resistance states. The input columns are connected...
7609085 Configurable integrated circuit with a 4-to-1 multiplexer  
Some embodiments provide a configurable integrated circuit with a tile. The tile has a first input multiplexer (IMUX), a second IMUX, and a look up table (LUT). The first IMUX is configured as a...
7605606 Area efficient routing architectures for programmable logic devices  
Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present...
7605604 Integrated circuits with novel handshake logic  
Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the...
7605603 User-accessible freeze-logic for dynamic power reduction and associated methods  
A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable...
7603599 Method to test routed networks  
Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources...
7603578 Programmable system on a chip for power-supply voltage and current monitoring and control  
A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital...
7602214 Reconfigurable sequencer structure  
A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is...
7602213 Using programmable latch to implement logic  
A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output,...
7602207 Quantum-dot cellular automata methods and devices  
A Quantum-dot Cellular Automata (QCA) device having normal QCA cells laid out in a planar structure such that there are a set of input lines, that may be columns, and a set of orthogonal, output...
7598768 Method and apparatus for dynamic port provisioning within a programmable logic device  
A method and apparatus to allow dynamic port provisioning of communication ports within a Programmable Logic Device (PLD). The dynamic port provisioning combines configuration of serial...
7596774 Hard macro with configurable side input/output terminals, for a subsystem  
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time...
7595659 Logic cell array and bus system  
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for...
7592835 Co-processor having configurable logic blocks  
A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically...
7592834 Logic block control architectures for programmable logic devices  
In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one...
7592833 Systems and methods involving field programmable gate arrays  
A method for programming logic in a field programmable gate array (FPGA) comprising, receiving a logic process including a logic node, and associating the node with a logic descriptor, and saving...
7592832 Adjustable transistor body bias circuitry  
An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the...
7589651 Flexible signal detect for programmable logic device serial interface  
A serial interface for a programmable logic device (PLD) uses an analog-to-digital converter (ADC) in place of conventional signal detect and receiver detect circuitry. A separate ADC can be used...
7589648 Data decompression  
In one embodiment, a data decompression circuit for a data stream having a repeated data word is provided. The data stream is compressed into a series of data frames such that the repeated data...
7589556 Dynamic control of memory interface timing  
Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and...
7589555 Variable sized soft memory macros in structured cell arrays, and related methods  
The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be...
7589552 Integrated circuit with redundancy  
Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks...
7586430 Integrated circuit comprising a mixed signal single-wire interface and method for operating the same  
The invention relates to an integrated circuit ( 1 ) which comprises a novel bidirectional mixed signal single-wire interface ( 6 ) via which the circuit receives command information from a host...
7586327 Distributed memory circuitry on structured application-specific integrated circuit devices  
A logic module for a structured ASIC is mask-programmable to perform any of a plurality of logic functions or to alternatively function as two static random access memory (“SRAM”) cells. Most...
7586326 Integrated circuit apparatus  
An integrated circuit apparatus includes a reconfigurable arithmetic operation device and a control device that generates mapping data defining a circuit configuration of the reconfigurable...
7583103 Configurable time borrowing flip-flops  
Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a...
7583102 Testing of input/output devices of an integrated circuit  
Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads...
7579869 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks  
A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks,...
7579866 Programmable logic device with configurable override of region-wide signals  
A programmable logic device architecture providing efficient configurable functionality to allow the “tie-off” of logic region-wide control signals. This functionality is provided while...
7579865 Selective loading of configuration data into configuration memory cells  
In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of...
7579864 Logic block control system and logic block control method  
The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the...
7579863 Circuit and method for reducing pin count of chip  
A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The...
7576564 Configurable IC with routing circuits with offset connections  
Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic...
7576561 Device and method of configuring a device having programmable logic  
A method of configuring a device having programmable logic is disclosed. The method comprises storing instructions in the device; selecting between one of the instructions stored in the device and...
7576558 Apparatus and method for enhanced readback of programmable logic device state information  
A method and apparatus is provided to significantly increase the flexibility of readback capture mechanisms, the apparatus being an integrated circuit device, comprising a configuration data router...
7576557 Method and apparatus for mitigating one or more event upsets  
A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the...
7574549 Bridge design for SD and MMC multiplexing  
A method for determining direction of signal transmission in a bi-directional signal line, including sampling data signals at two terminals, A and B, enabling data flow from A to B when data flow...
7573295 Hard macro-to-user logic interface  
A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first...
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