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7042263 Memory clock slowdown synthesis circuit  
Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and...
7042247 Programmable look-up tables with reduced leakage current  
The number of off and possibly leaking transistors in circuitry such as look-up table (LUT) circuitry is reduced by dividing the LUT or LUT-type circuitry into two separate or at least partly...
7042248 Dedicated crossbar and barrel shifter block on programmable logic resources  
A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one...
7038489 Method for sharing configuration data for high logic density on chip  
A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is...
7038952 Block RAM with embedded FIFO buffer  
A programmable logic device includes a block random access memory (“BRAM”) with an embedded first in, first out (“FIFO”) controller. Embedding the FIFO logic in silicon, rather than...
7038490 Delay-matched ASIC conversion of a programmable logic device  
An ASIC conversion of a programmable logic device (PLD) is provided. The PLD includes a plurality of logic blocks coupled together by a PLD routing structure. The ASIC includes a plurality of logic...
7034577 Variable timing circuit  
Systems and methods for delaying a signal by a selectable amount of time, wherein the selectable amount of time is adjustable in relatively small increments and wherein the variability of the...
7034570 I/O cell configuration for multiple I/O standards  
Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where...
7030659 Signal switch with reduced on resistance and undershoot protection  
An electronic switch applies ground potential to the backgate of a MOS pass transistor when the transistor is in the off state and the switch is open, during normal conditions. When the transistor...
7030648 High performance interconnect architecture for field programmable gate arrays  
This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of...
7026840 Programmable logic device  
A programmable logic device is provided with multiple power supplies such that, in one mode of operation, power can be disconnected from at least one part of the programmable logic device, while...
7028107 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)  
A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory...
7024579 Configurable timing system having a plurality of timing units interconnected via software programmable registers  
The timing system includes a plurality of timing units interconnected to perform a count operation. Software programmable registers interconnect the plurality of timing units, and a control circuit...
7023239 Automated boundary-scan chain composition method using a device database and access mechanism for storing and retrieving situation-dependent operation options  
A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically...
7023744 Reconfigurable SRAM-ROM cell  
Described are programmable logic devices with configuration memory cells that function both as RAM and ROM. A PLD incorporating these memory cells to store configuration data can be mask-programmed...
7019558 Conversion of configuration data to match communication protocol  
Various approaches for converting configuration data for programmable circuits are disclosed. In one embodiment, a first configuration bitstream is provided. The first configuration bitstream has a...
7020764 Semiconductor processing device  
A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit...
7012448 Integrated circuit and related improvements  
An improved integrated circuit and a related system apparatus and method. The integrated circuit includes a plurality of logic area or user logic areas; and an actively switchable network capable...
7009421 Field programmable gate array core cell with efficient logic packing  
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA...
7005889 Level shifting in a data processing apparatus  
A data processing apparatus and method are provided for controlling level shifting. The data processing apparatus comprises a first component provided within a first voltage domain and operable to...
7007264 System and method for dynamic reconfigurable computing using automated translation  
A system ( 20 ) for dynamic reconfigurable computing includes at least one microprocessor implemented on a field programmable gate array ( 10 ) having a programmable fabric ( 12 ). The system can...
7005887 Semiconductor integrated circuit  
A semiconductor integrated circuit is provided, which includes a first group of cells, in which a plural of I/O cells and/or power source cells for external input and/or output are arranged along a...
7003660 Pipeline configuration unit protocols and communication  
An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular...
7002370 Multiplexer configuration for programmable logic device  
A multiplexer is configured on a programmable logic device using a plurality of four-input look-up tables chained together. The required number of look-up tables is about one-half the number of...
7002368 Programmable logic device with high speed serial interface circuitry  
A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that...
6998871 Configurable integrated circuit for use in a multi-function handheld device  
A configurable integrated circuit includes at least one general purpose input/output (GPIO) interface module, a first functional module, and a second functional module. The GPIO interface module...
6996709 Method for configuring a configurable hardware block by configuring configurable connections provided around a given type of subunit  
A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type...
6992504 General-purpose logic array and ASIC using the same  
A general-purpose logic cell array includes a plurality of cells and a lower wiring layer. The plurality of cells are formed on a substrate, and each of the plurality of cells includes a plurality...
6992502 Configurable electronic circuit, in particular one dedicated to arithmetic calculations  
A configurable electronic circuit includes at least one tile that includes a plurality of cells interconnected. Each cell includes a multiplier, an arithmetic and logic unit for performing at least...
6989690 Methods of implementing scalable routing matrices for programmable logic devices  
Methods of implementing routing matrices for programmable logic devices (PLDs). Each method includes generating a seed matrix, a distribution matrix, adjustment values for the distribution matrix,...
6989687 Customizable and programmable cell array  
A logic array may include an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections...
6987401 Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods  
A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a...
6985011 Method of reducing the number of configuration bits by eliminating the unused configuration bits  
Apparatus and method configures a programmable logic device (PLD). The method includes reading a first configuration frame from the PLD. The first configuration frame indicates used and unused bit...
6982570 Reconfigurable device  
A reconfigurable device comprises tiles and an interconnect architecture. Each of the tiles comprises a circuit. The interconnect architecture couples to the circuit of each tile and comprises...
6980029 Programmable integrated circuit architecture  
A programmable logic device has a plurality of levels of programmable logic modules with fixed interconnections. The outputs of a level connect to inputs of the next level of programmable logic...
6980184 Display devices and integrated circuits  
Integrated circuits, assemblies with integrated circuits, display devices and electrical circuits. There are various different aspects and embodiments of these apparatuses described herein....
6981090 Multiple use of microcontroller pad  
A circuit arrangement permits a microcontroller wirebond pad to be configured to be an analog or digital input or output. The circuit arrangement uses any of a plurality of switching configurations...
6980031 Crosspoint switch with serializer and deserializer functions  
A programmable switch of three or more ports, each port having data lines separate from lines sharing control and addressing. The programmable switch includes internal logic control and electronic...
6977521 Field programmable gate array  
A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure....
6977520 Time-multiplexed routing in a programmable logic device architecture  
Programmable logic device interconnection resources include bus wires. A bus wire provides a programmable signal path across the programmable logic device from several logic device outputs to...
6976160 Method and system for controlling default values of flip-flops in PGA/ASIC-based designs  
During a reset condition or prior to system initialization of an FPGA-based system ( 100 ), a FPGA ( 102 ) can be pre-configured by loading a value from a memory cell ( 108 ) into at least one...
6975679 Configuration fuses for setting PWM options  
Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high...
6976102 Integrated circuit with auto negotiation  
Method and apparatus for auto-negotiation of a programmable logic device for any of a plurality of communication protocols is described. The programmable logic device is programmed for auto...
6972587 Built-in self repair for an integrated circuit  
An integrated circuit, such as a memory device, includes a built-in repair circuit. The repair circuit includes an on-chip source that produces a programming signal of sufficient duration and...
6973357 Method and configuration system for producing an application-specific functional module for a programmable controller  
A method and configuration system are used for producing an application-specific functional module from a predefined functional module for a programmable controller. In this context, a marking...
6972592 Self-timed scan circuit for ASIC fault testing  
A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch...
6972591 Semiconductor integrated circuit device having a semiconductor device with a modulatable gain coefficient  
An inverter circuit which is a representative example of the logic circuit includes a p-channel A-MOS transistor and an n-channel transistor. The gain coefficient β of the p-channel A-MOS...
6971004 System and method of dynamically reconfiguring a programmable integrated circuit  
The present invention system and method enables dynamic reconfiguration of an electronic device in a convenient and efficient manner. In one embodiment, the electronic device includes a...
6970015 Apparatus and method for a programmable trip point in an I/O circuit using a pre-driver  
The invention enables the performance of the input and output stages of an I/O circuit to be modified after an IC is manufactured. In one embodiment, the I/O circuit includes an output driver,...
6970014 Routing architecture for a programmable logic device  
An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”)....
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