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7098688 Regionally time multiplexed emulation system  
A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and...
7098687 Flexible routing resources in a programmable logic device  
In particular aspects, embodiments of the present invention provide a programmable logic device including routing paths from one routing resource to another via connections between outputs of...
7098686 System generated electromagnetic pulse guard  
A discharge guard circuit for use in combination with an integrated circuit that prevents the integrated circuit logic from damage or upset caused by system generated electromagnetic pulses at the...
7098685 Scalable serializer-deserializer architecture and programmable interface  
Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a...
7095248 Hardware and software programmable fuses for memory repair  
The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and...
7095247 Configuring FPGAs and the like using one or more serial memory devices  
The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration...
7092865 Method and apparatus for timing modeling  
Method and apparatus for timing modeling is described. More particularly, sub-processes for obtaining timing information are described. Each of these sub-process is limited to a portion of a gasket...
7088133 Programmable logic device with high speed serial interface circuitry  
A programmable logic device (“PLD”) includes high speed serial interface (“HSSI”) circuitry that can support several high speed serial (“HSS”) standards. Examples of the standards that...
7088136 Programmable logic device latch circuits  
Latch circuitry is provided for programmable logic regions on integrated circuits such as programmable logic device integrated circuits. A programmable logic device may have programmable logic...
7088135 Nonvolatile switch, in particular for high-density nonvolatile programmable-logic devices  
A nonvolatile switch has: an input terminal; an output terminal; a selection terminal; a first and a second biasing terminal; a memory element of flash type, having a first conduction region...
7088134 Programmable logic device with flexible memory allocation and routing  
A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into...
7086025 Programmable logic device partitioning method for application specific integrated circuit prototyping  
The interconnect pin count between field programmable gate arrays (FPGAS) used in prototyping an application specific integrated circuit (ASIC) is reduced without compromising the prototyping by...
7084664 Integrated circuits with reduced interconnect overhead  
Integrated circuits are provided that use on-chip data compression and decompression to minimize consumption of interconnect resources. Parallel-to-serial converter circuitry can use time-division...
7084665 Distributed random access memory in a programmable logic device  
Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user...
7084666 Programmable interconnect structures  
A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and...
7081772 Optimizing logic in non-reprogrammable logic devices  
A method for reducing the amount of logic needed to perform logic operations in non-reprogrammable logic devices based on preexisting circuit designs is provided. The logic optimization method...
7081771 Upgradeable and reconfigurable programmable logic device  
Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable...
7081773 Updating configuration for programmable logic device  
A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from...
7078936 Coupling of signals between adjacent functional blocks in an integrated circuit chip  
A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply...
7078932 Programmable logic device with reduced power consumption  
The present invention provides a programmable logic device with reduced power consumption comprising, a first set of data storage elements, at least a first power supply connected to the said first...
7080226 Field programmable gate array (FPGA) configuration data path for module communication  
Data is transferred on a field programmable gate array (FPGA) by (1) retrieving a first set of data from a first block RAM column of a configuration memory of the FPGA, (2) storing the first set of...
7075331 Methods and systems for providing hardware assisted programming of a programmable logic device in an embedded system  
A programmable logic device (PLD) in a microprocessor system is programmed with minimal load on system resources. A microprocessor reads programming data from a first memory using a parallel bussed...
7075333 Programmable circuit optionally configurable as a lookup table or a wide multiplexer  
Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is...
7075334 Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks  
The apparatus comprises a repeatable non-uniform segmented routing architecture in a field programmable gate array having a plurality of sets of routing tracks having a first and last track...
7075332 Six-input look-up table and associated memory control circuitry for use in a field programmable gate array  
A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. Sixty-four write control circuits are coupled to the 64 memory cells. A first write address decoder...
7071733 Cross-bar matrix for connecting digital resources to I/O pins of an integrated circuit  
A matrix of routing cells forming a cross-bar decoder ( 310 ). Signal triplets are coupled through the cross-bar decoder ( 310 ) based on control by a microprocessor. A register ( 50 ) provide...
7071732 Scalable complex programmable logic device with segmented interconnect resources  
A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and...
7071729 Dual-purpose shift register  
A serial shift register and method for simultaneously storing bits of data and a serially advancing pointer is provided. In one embodiment, each stage of the shift register may have only two...
7071730 Voltage level translator circuitry  
Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage protection circuitry to ensure that...
7068068 Re-configurable mixed-mode integrated circuit architecture  
An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured...
7068071 Integrated circuit with overclocked dedicated logic circuitry  
An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal...
7068069 Control circuit and reconfigurable logic block  
A control circuit for providing a control signal to build a logic circuit includes a latch circuit including first and second inverted logic gates; a first variable resistive memory provided...
7068070 Customizable and programmable cell array  
A semiconductor device may include a logic array having a multiplicity of inputs and a multiplicity of outputs and customized interconnections providing permanent direct interconnections among at...
7064577 Method and apparatus for supporting variable speed configuration hardware  
A programmable logic device (PLD) includes a plurality of programmable resources. The PLD includes configuration hardware that configures a first programmable resource at a first rate and a second...
7064578 Distributed bus structure  
A programmable logic device includes a routing structure, which takes the form of multiple distributed OR gates, which are positioned within the device to allow signals to be input from spaced...
7064579 Alterable application specific integrated circuit (ASIC)  
A highly economical alterable ASIC contains multiple fully optimized custom ASIC designs in one IC foot-print, each design utilizing the entire IC. The user can switch between multiple...
7065732 Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane  
A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is...
7061267 Page boundary detector  
A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean...
7061275 Field programmable gate array  
A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure....
7061271 Six-input look-up table for use in a field programmable gate array  
A 6-input LUT architecture includes 64 memory cells, which store 64 corresponding data values. A set of 64 transmission gates is configured to receive the 64 four data values. A first input signal...
7058131 Signal transmission system with programmable voltage reference  
A high speed signal transmission system employs differential receivers for receiving data signals transmitted over circuit transmission lines. One input each receiver is coupled to the output of a...
7057413 Large crossbar switch implemented in FPGA  
A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch,...
7057412 Configurable crossbar switch  
A configurable crossbar switch is provided between the signaling I/O and the IP block in a programmable logic resource. A programmable logic resource receives input data via an I/O port. This data...
7058177 Partially encrypted bitstream method  
It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method...
7053651 Low power CMOS switching  
A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line,...
7054967 SRAM bus architecture and interconnect to an FPGA  
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of...
7049845 Programmable delay line using configurable logic block  
A configurable logic block (“CLB”) in a programmable logic device (“PLD”), such as a complex programmable logic device (“CPLD”) or a field programmable gate array (“FPGA”), routes a...
7046034 Programmable logic device having heterogeneous programmable logic blocks  
A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry...
7047166 Method and VLSI circuits allowing to change dynamically the logical behavior  
A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The...
7042263 Memory clock slowdown synthesis circuit  
Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and...
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