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7584370 |
Circuits, switch assemblies, and methods for power management in an interface that maintains respective voltage differences between terminals of semiconductor devices in open and close switch states and over a range of voltages
A semiconductor network is interposed between first and second multiple-port interfaces each having high-voltage, intermediate-voltage and ground ports to form a switch assembly. The assembly...
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7511535 |
Fine-grained power management of synchronous and asynchronous datapath circuits
A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least...
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7451384 |
Error recovery in asynchronous combinational logic circuits
A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results...
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7276932 |
Power-gating cell for virtual power rail control
Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and...
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7133949 |
Distributed switching method and apparatus
Switching method and apparatus for assigning a communication grant to a first processing unit in a communication network comprising a plurality of processing units, each processing unit being...
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7129742 |
Majority logic circuit
A novel majority logic circuit is disclosed to determine whether the majority of the inputs are a one, within a constant number of clock cycles, regardless of the number of inputs. The majority...
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7129741 |
Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit
This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design...
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7051127 |
Method and apparatus for selectively providing data pre-emphasis based upon data content history
The present invention comprises a method and apparatus for selectively providing pre-emphasis to the output of a first driver during an initial portion of certain data transitions while...
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7042246 |
Logic circuits for performing threshold functions
Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at...
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7036018 |
Integrated security circuit
An integrated security circuit, for example, a microcontroller for smart cards, includes a function unit executing a security function. A control device determines the number of executions of the...
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6907534 |
Minimizing power consumption in pipelined circuit by shutting down pipelined circuit in response to predetermined period of time having expired
Power consumption in a circuit is minimized. The circuit includes a pipelined circuit having a plurality of stages. A determination is made as to whether a predetermined period of time has expired....
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6900658 |
Null convention threshold gate
A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of...
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6888748 |
Programmable circuit and its method of operation
A programmable circuit and its method of operation are disclosed in which a transistor is used as a programmable element. The transistor may be programmed to one of two different gate threshold...
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6848094 |
Netlist redundancy detection and global simplification
A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist,...
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6828821 |
Input buffer circuit
An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage...
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6798247 |
Output buffer circuit
An output buffer circuit disclosed herein includes a buffer supplied with an input signal and outputting an output signal from an output terminal; a driving assistant buffer including a first...
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6741100 |
Semiconductor integrated circuit capable of high-speed circuit operation
In a standard cell, rise time when an output transitions from a low-level voltage to a high-level voltage and fall time when an output transitions from the high-level voltage to the low-level...
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6646464 |
Data hold circuit, a semiconductor device and a method of designing the same
A semiconductor integrated circuit technology that does not invite the drop of α-ray resistance of flip-flop circuits even when devices are miniaturized. A data hold circuit according to this...
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6608499 |
Method for compensating a threshold voltage of a neighbor bit
A method for compensating a threshold voltage of a neighbor bit, are provided. The method includes the first step of arbitrating the word line voltages applied to bits demanded to be programmed,...
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6486700 |
One-hot Muller C-elements and circuits using one-hot Muller C-elements
A one-hot Muller C-element, wherein an event received on each of a plurality of inputs results in an event being output, can be implemented with complementary inputs and a true transistor pair...
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6470328 |
Artificial neuron on the base of B-driven threshold element
A synapse element consisting of a smaller number of elements utilizing common semiconductor technology, and a neuron circuit and a neuron device using the synapse elements are provided. The synapse...
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6430585 |
Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof
A logic gate, an adder and methods of operating and manufacturing the same. In one embodiment, the logic gate includes: (1) a summer, having at least two single-bit inputs and a noise-suppression...
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6384624 |
Logical operational circuit using two stage neumos circuits
The present invention has as an object thereof to provide a logical operational circuit which is capable of realizing, with present semiconductor manufacturing technology, logical functions, the...
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6333640 |
Asynchronous logic with intermediate value between data and null values
A switching element and method for asynchronous logic switches an output signal according to a switching-logic relationship between or among input signals. Input signals may assume at least a DATA...
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6320409 |
CMOS majority circuit
A majority circuit comprises CMOS circuits is adapted to prevent operation errors due to disagreement of conductance among the transistors of the circuits. Such a majority circuit can realize a...
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6313660 |
Programmable gate array
A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality...
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6262593 |
Semi-dynamic and dynamic threshold gates with modified pull-up structures
An m-of-n threshold gate is disclosed having an output stated derived from the voltage of a signal node. A "Go-to-Data" circuit pulls the signal node to a first state, corresponding to an ASSERTED...
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6255855 |
Integrated circuit having a decoder
An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first...
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6253348 |
Hardware design for majority voting, and testing and maintenance of majority voting
The invention relates to majority voting testing. A number of input signals are monitored individually by separate monitors, one monitor for each signal. Each monitor generates a control signal...
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6205458 |
Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
A circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit...
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6118297 |
Voting circuit and method
A voting circuit (34) comprises a first variable delay (60) operable to receive a first set of signals in a clock signal and to determine a first delay based on the first set of signals. The first...
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6078190 |
Threshold logic with improved signal-to-noise ratio
The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting...
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6043674 |
Null convention logic gates with flash, set and reset capability
Threshold logic gates are disclosed that respond to signals that may assume at least a first state having an arithmetic or logic meaning, and a second NULL state that has no arithmetic or logic...
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6020754 |
Look up table threshold gates
A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate...
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5942912 |
Devices for the self-adjusting setting of the operating point in amplifier circuits with neuron MOS transistors
A defined zero point voltage (V 0 ), dependent on a settable zero point voltage target value (V 0 ,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k)....
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5917338 |
Area-efficient implication circuits for very dense Lukasiewicz logic arrays
A one-diode circuit for negated implication (.about.➝) is derived from a 12-transistor Lukasiewicz implication circuit (➝). The derivation also yields an adjustable three-transistor implication...
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5905387 |
Analog voltage-signal selector device
The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first...
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5838166 |
Compact and high-speed judging circuit using misfets
To judge whether or not the number of high-level bits among N (N≤2) bits of an input signal is greater than a predetermined number M (1≤M<N), a judging circuit has a differential amplifier,...
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5828228 |
Null convention logic system
A NULL convention logic element comprises an input, an output and a threshold switching circuit. The input receives NULL convention signals that are encoded onto a plurality of physical input...
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5784386 |
Fault tolerant synchronous clock distribution
There is provided a fault tolerant clock system for a synchronous design using N-way combinatorial voting schemes for N greater than 3. The system comprises a plurality of clock circuits for...
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5764081 |
Null convention interface circuits
An interface circuit between NULL Convention Logic and non-NULL convention memory includes: a first conversion circuit which converts NULL convention address signals to non-NULL address signals. A...
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5694054 |
Integrated drivers for flat panel displays employing chalcogenide logic elements
The present invention defines a display driver for driving a flat panel display having rows and columns. The display driver has row and column drivers comprised of logic gates where each logic gate...
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5677637 |
Logic device using single electron coulomb blockade techniques
A memory device includes a memory node (2) to which is connected a tunnel barrier configuration such that the node exhibits first and second quantized memory states for which the level of stored...
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5644253 |
Multiple-valued logic circuit
There are provided n operation circuits in a multiple-valued logic circuit which receives plural multiple-valued input logic signals corresponding to respective numeral values and outputs a...
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5467429 |
Neural network circuit
A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight...
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5455519 |
Josephson logic circuit
A Josephson logic circuit includes a Josephson element inserted between an input terminal and a reference electric potential such as ground, a resistor inserted between the input terminal and an...
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5424773 |
Apparatus and method for generating a pseudo camera position image from a plurality of video images from different camera positions using a neural network
The present invention generates a plurality of video image data of different camera positions for an object shot by a camera and modifies and synthesizes the video image data of a pseudo camera...
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5422982 |
Neural networks containing variable resistors as synapses
A synthetic neural network having a plurality of neuronal elements arranged in an input layer, an output layer, and a hidden layer between the input layer and the output layer. The network has a...
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5414718 |
Three-input poller
A poller including an output (S), as well as a first (E1), a second (E2), and a third (E3) input, receiving respectively a first (E s 1), a second (E s 2), and a third (E s 3) signal, which are...
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5386424 |
Apparatus and method for transmitting information between dual redundant components utilizing four signal paths
An apparatus and method for transmitting information between dual redundant components comprises two information sources each of which is coupled to two transmitters, the outputs of which are...
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