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7609799 Circuit, system, and method for multiplexing signals with reduced jitter  
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer...
7583753 Methods and transmitters for loop-back adaptive pre-emphasis data transmission  
A method of transmitting data can include pre-emphasizing data for transmission by a transmitter over a transmission line based on an error feedback signal provided to the transmitter from a...
7436214 Pseudo differential current mode receiver  
A pseudo differential current mode receiver includes a regulated cascode buffer for buffering a received data current to generate a buffered data current with cascode-reduced input impedance and...
7409659 System and method for suppressing crosstalk glitch in digital circuits  
A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk...
7394281 Bi-directional universal serial bus booster circuit  
A bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting...
7339396 Method and apparatus for ameliorating the effects of noise generated by a bus interface  
A method and apparatus for ameliorating the effects of noise generated by a bus interface provides improved performance of integrated circuits having other circuits sensitive to the transient noise...
7332930 Noise canceller circuit  
A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes...
7323907 Pre-emphasis driver control  
Embodiments for controlling pre-emphasis driver circuits for electrical signal interconnects within a computer system are disclosed.
7315182 Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control  
A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit...
7233164 Offset cancellation in a multi-level signaling system  
A receive circuit having a sampling circuit and a threshold generating circuit. The sampling circuit generates a first sample value having either a first state or a second state according whether...
7218135 Method and apparatus for reducing noise in a dynamic manner  
An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring...
7170312 Systems and methods for reducing timing variations by adjusting buffer drivability  
Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers...
7143381 Resonance reduction arrangements  
Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined...
7116126 Intelligent delay insertion based on transition  
A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the...
7091741 Input buffer capable of reducing input capacitance seen by input signal  
Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input...
6925559 Reducing effects of transmission line reflections by changing transmission line pedestal voltage or recever threshold voltage while monitoring for irregular synchronization  
A system and method of reducing an effect of signal distortion from reflection on a transmission line include changing at least one of a pedestal voltage level on the transmission line and a signal...
6876224 Method and apparatus for high speed bus having adjustable, symmetrical, edge-rate controlled, waveforms  
A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are...
6873178 Skewed bus driving method and circuit  
Circuits and methods for driving buses (data buses or address buses) which provide a reduction in interference such as crosstalk between adjacent bus lines of a bus, even as the width of the bus...
6870389 Differential circuit with current overshoot suppression  
A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair Q 5 and Q 6 having a tail current...
6842044 Glitch-free receivers for bi-directional, simultaneous data bus  
A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two...
6794893 Pad circuit and method for automatically adjusting gain for the same  
A pad circuit and operating method for automatically adjusting gains is disclosed, wherein the pad circuit is embedded in an integrated circuit chip that further includes a core logic circuit...
6703869 Method and apparatus for low latency distribution of logic signals  
A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an...
6675331 Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch  
A transparent latch ( 18 ) and a logic conditioning circuit ( 10 ) are disclosed. The transparent latch ( 18 ) receives signals from conditioning circuit ( 10 ), including a test input that...
6661255 Interface circuit  
An interface circuit for a printer to prevent transmission of an incorrect control signal when power is input into the printer. The interface circuit improves the stability of the printer at the...
6563344 Buffer circuit for the reception of a clock signal  
A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit...
6549033 Signal processing device and process and electrical apparatus comprising such a device  
The signal processing device comprises determining means to supply an output signal having a value representative of a time constant of a part of an input signal having an appreciably exponential...
6542003 Circuit configuration and method for directly electrically isolated broadband transmission  
In order to enable a simple and cost-effective directly electrically isolated transmission of data signals, the data signals are superposed on a clock signal in an input stage and are transmitted...
6515512 Capacitively coupled re-referencing circuit with transient correction  
A re-referencing circuit for re-referencing a digital input signal from a first logic environment to a second logic environment includes a non-inverting circuit having a non-inverting transfer...
6476640 Method for buffering an input signal  
A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal...
6429690 Programmable linear transconductor circuit  
A programmable linear transconductor circuit is disclosed. The programmable linear transconductor circuit includes a first current source and a second current source, a first group of transistors...
6351158 Floating gate circuit for backwards driven MOS output driver  
A bus driver circuit has floating gate circuits with three transistors. Two of the transistors for an inverter for operating the output power transistor. The third transistor is connected to...
6184717 Digital signal transmitter and receiver using source based reference logic levels  
A signal transmitter for transmitting digital logic signals and a complementary receiver, are disclosed. The signal transmitter comprises a plurality of signal drivers and at least one reference...
6137306 Input buffer having adjustment function for suppressing skew  
An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted...
6094062 Coupled noise reduction circuitry  
Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power...
6091265 Low voltage CMOS input buffer with undershoot/overshoot protection  
Method and circuitry for implementing low voltage input buffers using low voltage CMOS transistors are disclosed. Various novel circuit techniques enable the input buffer to safely receive and...
5990700 Input buffer circuit and method  
An input buffer circuit includes a plurality of paths having a different threshold voltage, respectively, a comparator for comparing an output value of the paths, a switch for determining operation...
5949248 Apparatus and method for dynamic hardening of a digital circuit  
A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66)...
5910736 Differential-type data transmitter  
A differential-type data transmitter includes a differential amplifier pair (T1, T2, T4, T6, T8) having a plurality of transistors and receiving a pair of a first input signal and a second input...
5894229 Input circuit of semiconductor memory device for generating an internal signal in accordance with an external signal and for applying it to an internal circuitry  
In a DRAM, first and second P channel MOS transistors are connected in series between an output node of an NOR gate of an input buffer and a power supply line. The first P channel MOS transistor...
5612630 Asynchronous self-adjusting input circuit  
An asynchronous self-adjusting circuit includes an input circuit receiving an input signal and providing an output signal. The input circuit starts to switch the output signal to a first logic...
5565803 Digital input threshold switching circuit  
A digital input circuit including a first digital buffer for receiving a digital data signal and for providing a first buffered digital data output, the first digital buffer having a first...
5539337 Clock noise filter for integrated circuits  
A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to...
5517140 Sample and hold circuit  
A sample and hold circuit has an analog switch, a hold capacitor, a voltage-follower type operational amplifier, and a ringing cancel circuit. The ringing cancel circuit is interposed between a...
5349246 Input buffer with hysteresis characteristics  
An input buffer circuit is disclosed which has feedback hysteresis transistors having similar size characteristics as the drive transistors. The drive transistors are located in a first inverting...
5336948 Active negation emulator  
An active negation emulator circuit for improving the noise margin of signals carried by a signal interface bus. The circuit includes a sensor for sensing the voltage on the bus and a variable...
5315176 Differential ECL circuit  
A differential ECL (emitter coupled logic) circuit, with differential inputs and output and no series gates, comprises a plurality of transistor pairs. The differential ECL circuit can operate at...
5220211 High speed bus transceiver with fault tolerant design for hot pluggable applications  
A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each...
5111074 Multi-input compound function complementary noise-immune logic  
A digital logic circuit having multiple inputs and a product-of-sums output uses multi input OR circuits with interacting constant-current and constant-voltage elements to improve voltage transfer...
5041743 Emitter-follower circuit with reduced delay time  
The emitter-follower circuit of the invention, having a current-switching type logic circuit operating between the ground potential and the first negative power supply potential, comprises an...
5034632 High speed TTL buffer circuit and line driver  
A non-inverting TTL buffer circuit provides an input for receiving data signals at high and low potential levels and an output for transmitting data signals in phase with the input. The base node...
Matches 1 - 50 out of 105 1 2 3 >