|
Match
|
Document |
Document Title |
|
|
7428465 |
Testing control methods for use in current management systems for digital logic devices
Systems and methods for Current Management of Digital Logic Devices are provided. In one embodiment a method for calibrating a digital logic circuit current management system is provided. The...
|
|
|
7427872 |
Asynchronous coupling and decoupling of chips
In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second...
|
|
|
7421530 |
Noise attenuating bus structure and method for a mobile communication
A bus structure of a mobile communication terminal for reducing digital noise is disclosed. The bus structure comprises a bus switch controller, a first element having a first bus, a second element...
|
|
|
7411416 |
Technology for supressing noise of data bus circuit
A data bus circuit connects a south bridge driven by a first voltage and a bay driven by a second voltage. The first voltage and the second voltage are different. The data bus circuit includes a...
|
|
|
7405598 |
Differential line compensation apparatus, method and system
A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second...
|
|
|
7405591 |
Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage
An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver...
|
|
|
7397270 |
Dynamically-adjustable differential output drivers
Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output...
|
|
|
7394282 |
Dynamic transmission line termination
A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some...
|
|
|
7388400 |
Semiconductor integrated circuits with power reduction mechanism
A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power...
|
|
|
7385415 |
Semiconductor integrated circuit
A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic...
|
|
|
7382152 |
I/O interface circuit of integrated circuit
A plurality of transistor pairs of Pch and Nch transistors are connected in series between VDD and GND. An I/O terminal is connected to each connection point of the transistor pairs. Two transistor...
|
|
|
7380182 |
Method and apparatus for checking output signals of an integrated circuit
Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated...
|
|
|
7372293 |
Polarity driven dynamic on-die termination
Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output...
|
|
|
7372291 |
Circuits having precision voltage clamping levels and method
A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also...
|
|
|
7362130 |
Method and device for transmission with reduced crosstalk
The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat...
|
|
|
7332932 |
Serial link receiver with wide input voltage range and tolerance to high power voltage supply
A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a...
|
|
|
7332930 |
Noise canceller circuit
A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes...
|
|
|
7323901 |
Semiconductor integrated circuit device
A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an...
|
|
|
7315182 |
Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control
A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit...
|
|
|
7305038 |
Peripheral device receiver detection in a high noise environment
A peripheral device includes a data port having high and low impedance terminations, a transmitter having a data signal generator and a receiver detector. The data signal generator is electrically...
|
|
|
7295033 |
Impedance adjustment circuits and methods using replicas of variable impedance circuits
An impedance adjustment circuit for controlling an impedance of a variable impedance circuit includes a calibration circuit including a replica of the variable impedance circuit and configured to...
|
|
|
7285978 |
Circuit and method for impedance calibration of output impedance of LVDS driver
An H-bridge LVDS driver circuit includes a means to calibrate the output impedance of the switches of an LVDS driver to any desired value.
|
|
|
7282947 |
Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches...
|
|
|
7282946 |
Delay-insensitive data transfer circuit using current-mode multiple-valued logic
The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission...
|
|
|
7279924 |
Equalization circuit cells with higher-order response characteristics
Equalization circuitry includes additional components to boost the performance of the circuitry to a higher-order response. The additional components are preferably controllably variable so that...
|
|
|
7242214 |
Semiconductor integrated circuits with power reduction mechanism
Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within...
|
|
|
7215136 |
Semiconductor integrated circuits with power reduction mechanism
Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within...
|
|
|
7180325 |
Data input buffer in semiconductor device
A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second...
|
|
|
7170438 |
Decision feedback equalizer with bi-directional mode and lookup table
In one embodiment, a decision feedback equalizer helps mitigate intersymbol interference in a bi-directional signaling environment. In the particular embodiment, the decision feedback equalizer...
|
|
|
7170312 |
Systems and methods for reducing timing variations by adjusting buffer drivability
Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers...
|
|
|
7167017 |
Isolation cell used as an interface from a circuit portion operable in a power-down mode to a circuit portion in a power-up mode
An isolation cell provided between a first module (which can operate in either a power-up mode or a power down mode) and a second module. According to an aspect of the present invention, the...
|
|
|
7161385 |
Circuit elements and parallel computational networks with logically entangled terminals
The invention relates to circuit elements and computing networks for resolving logical entanglement, in which the allowed logical value of a variable in a set of variables depends on the logical...
|
|
|
7161379 |
Shunted current reduction
One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or...
|
|
|
7142006 |
Device and method to cause a false data value to be correctly seen as the proper data value
The present invention is a device and method to change the reflection time of a bidirectional signal so as to cause a false data value to be correctly seen as the proper data value when the...
|
|
|
7142005 |
Method and apparatus for a reference clock buffer system
According to one example embodiment, a buffer, e.g., in a clock/signal distribution apparatus is provided that substantially reduces jitter due to power supply noise. Decoupler and input stage...
|
|
|
7133956 |
Electronic device with serial ATA interface and signal amplitude adjusting method
The CPU of an electronic device generates a parameter for determining the amplitude of a serial data signal when it is output from an output device to a serial ATA bus. The parameter indicates a...
|
|
|
7129740 |
Low noise output buffer
The strength of the output buffer is changed gradually when there is a transition in the output (or input) value. Due to the gradual change, switching noise is avoided in several contexts (e.g.,...
|
|
|
7127629 |
Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal
A method and apparatus for redriving a data signal adjusts a sampling clock signal responsive to the data signal. An embodiment of an I/O cell may include a receiver to receive and redrive a data...
|
|
|
7116126 |
Intelligent delay insertion based on transition
A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the...
|
|
|
7099786 |
Signaling accommodation
A receiving unit may implement voltage compensation using a parameters table, an analog calibration component, and/or a digital calibration component. In certain implementation(s), an integrated...
|
|
|
7091741 |
Input buffer capable of reducing input capacitance seen by input signal
Provided is an input buffer whose input capacitance presented to input signals can be reduced. The input buffer includes a first differential amplifier which compares the sizes of a first input...
|
|
|
7088129 |
Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers
A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each...
|
|
|
7084662 |
Variable impedance output driver
A variable impedance output driver has been disclosed. One embodiment of the variable impedance output driver includes a first pull-up structure, a pull-down structure, and a comparator, coupled to...
|
|
|
7075329 |
Signal isolators using micro-transformers
A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal,...
|
|
|
7071727 |
Method and apparatus for mitigating radio frequency radiation from a microprocessor bus
A low-pass filter 10 on a microprocessor bus 22 for attenuating radio frequencies from digital signals travelling on the bus 22 from a microprocessor 12 to a peripheral device 20 . An RC...
|
|
|
7053651 |
Low power CMOS switching
A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line,...
|
|
|
7038486 |
Semiconductor integrated circuit device
A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an...
|
|
|
7034566 |
Method and circuit for increased noise immunity for clocking signals in high speed digital systems
Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a...
|
|
|
7024496 |
Operation method of input/output pad with monitoring ability
An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit. When it is...
|
|
|
7023237 |
Semiconductor integrated circuits with power reduction mechanism
Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within...
|