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7616024 |
Resilient integrated circuit architecture
The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of...
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7576557 |
Method and apparatus for mitigating one or more event upsets
A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the...
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7550991 |
Configurable IC with trace buffer and/or logic analyzer functionality
Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits for configurably performing different operations and several user design...
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7499676 |
Low voltage differential signaling transceiver
A low voltage differential signaling transceiver includes a transmitter and a receiver, the transmitter having a first terminal in signal communication with a transmission line, a source resistance...
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7427872 |
Asynchronous coupling and decoupling of chips
In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second...
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7424642 |
Method for synchronization of a controller
A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary...
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7423448 |
Radiation hardened logic circuit
A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an...
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7397269 |
Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal
Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB 1 has...
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7397268 |
Receiver circuit
In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection...
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7386826 |
Using redundant routing to reduce susceptibility to single event upsets in PLD designs
Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing...
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7345502 |
Design security for configurable devices
Methods and structures for design security in configurable devices are described. In some embodiments, a configurable device may be placed in an unsecured mode allowing for access to configuration...
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7301362 |
Duplicated double checking production rule set for fault-tolerant electronics
Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to...
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7265574 |
Fail-safe method and circuit
A method and a circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, comprising a first inverter stage providing a constant...
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7250786 |
Method and apparatus for modular redundancy with alternative mode of operation
A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting...
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7236003 |
H-bridge circuit with shoot through current prevention during power-up
The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices...
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7236002 |
Digital CMOS-input with N-channel extended drain transistor for high-voltage protection
A circuit and a method are given, to realize an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a...
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7236001 |
Redundancy circuits hardened against single event upsets
A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as...
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7235999 |
System monitor in a programmable logic device
Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or...
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7224178 |
Circuit re-synthesis and method for delay variation tolerance
By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in...
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7215135 |
Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions
An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes...
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7187991 |
Failsafe control circuit for electrical appliances
Failsafe control circuit for electrical appliances whereby at least one electrical load ( 10 ) is activated, the control circuit comprising logic control means ( 1 ), operation switching means ( 8...
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7142004 |
Radiation hardening of logic circuitry using a cross enabled, interlocked logic system and method
A system and method for hardening a logic circuit against radiation-event effects is provided. The system may include a logic circuit, first and second feed-forward devices, and first and second...
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7135885 |
Dynamically adjustable signal detector
A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold...
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7123458 |
Method and circuit arrangement for protecting an electric motor from an overload
A method and a circuit for protecting an electric motor and/or its trigger circuit against overload in the emergency-operation mode in a motor vehicle direct-current fan motor operated by means of...
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6995601 |
Fuse state detection circuit
A fuse state detection circuit ( 300 ) has a reference circuit part ( 302, 302 ′) and a fuse detection circuit part ( 308, 308 ′), the reference circuit part ( 302, 302 ′) having a fuse (...
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6980023 |
Dynamically adjustable signal detector
A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold...
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6965250 |
Reduced delay power fail-safe circuit
An improved power fail-safe has an effective maximum delay of two gate delays from an input operably powered by a first power supply to a first and a second output operably powered by a second...
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6960930 |
Method and apparatus for determining the minimum or maximum switching activity of a digital circuit
In order when designing a digital circuit to be able to determine the minimum or maximum switching activity for estimating the power consumption it is determined according to the invention on the...
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6958622 |
Scan-mode indication technique for an integrated circuit
An integrated circuit and method for indicating the integrated circuit to enter into a scan mode are disclosed. A designated signal, such as an analog supply signal, for an analog block of an...
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6954083 |
Circuit for detection of hardware faults due to temporary power supply fluctuations
Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault...
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6933745 |
Bus network interface
A system and method for transmitting data includes one or more transmitters connected to each of at least one bus data line via open-driver bus data line drivers, and one or more receivers. In a...
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6928132 |
Methods and apparatus for operating a system
A method for operating a system having a plurality of modes and interlocks between the modes is provided. The method includes operating the system in a first mode and switching the system to a...
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6927599 |
Failsafe for differential circuit based on current sense scheme
A system and method are described for receiving differential currents in a current mode circuit. When conditions occur where the receiver inputs are floating, undriven, shorted together, or one or...
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6815978 |
Single clock source for plural scan capture chains
A clock signal is applied to a clock pin of an integrated circuit. The clock signal is coupled from the clock pin to a first scan chain in a first time period without coupling the clock signal to a...
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6791362 |
System level hardening of asynchronous combinational logic
A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two...
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6788097 |
Security improvements for programmable devices
A programmable logic device includes a function block to generate a power control signal that is distributed on a rail to selectively power down various components on the device. The rail is...
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6781456 |
Failsafe differential amplifier circuit
Differential input fail safe circuitry is disclosed that detects missing or too low differential signals combined with a frequency lower than a frequency limit where a final safe condition is...
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6756808 |
Clock edge detection circuit
The clock edge detection circuit is equipped with a first delay circuit 11 that delays a first clock signal and outputs a first delay clock signal, a second delay circuit 21 that delays a...
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6731131 |
Circuit for an electronic semiconductor module
It is an aim to reduce an area required on a chip for interconnects which cross a spine center. The circuit has n inputs, which are disposed on one side of the spine center. An encoder is...
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6719388 |
Fail-safe circuit for dynamic smartpower integrated circuits
A method and Apparatus for protection of semiconductor micromechanical devices that use circuits with dynamic logic addressing is disclosed. In one exemplary embodiment of the invention, a...
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6696851 |
Reception line break detection apparatus
A reception line break detection apparatus includes a transmission-side line drive, a reception line, a switching element, and a reception-side line receiver receiving signals transmitted from the...
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6674319 |
Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines
A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential...
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6670823 |
Detecting counter contents for time-critical applications
An additional bit is used in a binary register for detecting register contents in timing and counting applications. A predetermined timing or counting event occurs when the additional bit changes...
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6624654 |
Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets
Methods for implementing a circuit in a programmable logic device (PLD) that protect the circuit from the effects of single event upsets. When routing nodes within the circuit using the...
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6570401 |
Dual rail power supply sequence tolerant off-chip driver
The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The...
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6563335 |
Semiconductor device and test method therefor
A semiconductor device and a test method therefor can perform delay evaluation without depending on a chip size and a measuring unit. An input I/O circuit and an output I/O circuit are disposed on...
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6563322 |
Method and apparatus for detecting open circuit fault condition in a common-mode signal
The present invention relates to an apparatus and a method for detecting an open circuit fault condition in a differential signal, and generating a fault detection signal. An open circuit fault...
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6529032 |
Methods and apparatus for full I/O functionality and blocking of backdrive current
An input/output (I/O) port designed for electrical interconnection with multiple similar ports includes an input read circuit, an output drive circuit, and a circuit to control the port for input...
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6522168 |
Interface latch for data level transfer
An interface for translating data of different voltages includes an input terminal structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as...
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6504410 |
Fault tolerant storage cell
A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of...
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