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7504850 Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit  
Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter ( 3 I),...
7474116 Latch circuit  
A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input...
7423448 Radiation hardened logic circuit  
A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an...
7411412 Semiconductor integrated circuit  
A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection...
7277346 Method and system for hard failure repairs in the field  
A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit...
7215135 Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions  
An apparatus for hardening logic circuitry against a Single-Event-Effect condition and for providing immunity to an overshoot and undershoot condition is provided. The apparatus includes...
6809545 Programmable power adjust for microelectronic devices  
A circuit to adjust power is disclosed. The circuit comprises at least one pass gate and a power adjustor electrically coupled to each pass gate such that the power adjustor consumes power when the...
6801051 System and method for providing capacitive spare fill cells in an integrated circuit  
A processor includes an integer unit operable to execute integer instructions and a floating point unit operable to execute floating point instructions. The processor also includes at least one...
6794925 Cold spare circuit for CMOS output circuit  
A first cold spare circuit has first and second transistors, and a second cold spare circuit has third and fourth transistors. The first transistor has a gate controlled by a function of a first...
6756809 Single event upset immune logic family  
A collection of logic gates that provide single event upset (SEU) immunity. The family of gates include an inverter, a two-input NOR gate, a two-input NAND gate, a three-input AND-NOR gate, and a...
6703858 Logic architecture for single event upset immunity  
An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and...
6486695 Protecting unit  
A protecting unit is provided. The protecting unit can prevent accidents from occurring that become problems when data are transmitted due to for instance LVDS and for instance laser light is...
6320405 Circuit for the switching of loads  
An apparatus for switching loads, based on a starting signal, having a first MOSFET output stage and a second downstream MOSFET output stage, each of the MOSFET output stages being controllable by...
6316956 Multiple redundant reliability enhancement method for integrated circuits and transistors  
In a fault-tolerant integrated power circuit, a plurality of power transistors, each having a power source electrically coupled to a common source line, a power gate and a power drain electrically...
6278287 Isolated well transistor structure for mitigation of single event upsets  
CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of...
6236241 Redundant decoder having fuse-controlled transistor  
A redundant decoder having fuse-controlled transistor comprises as follows: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an...
6175938 Scheme for the reduction of extra standby current induced by process defects  
A scheme for reduction of extra standby current induced by process defects is disclosed. After the bit lines and cells with failure due to process defects are repaired by using redundancy in the...
6125069 Semiconductor memory device with redundancy circuit having a reference resistance  
A semiconductor memory device with a redundancy circuit includes a reference section, a fuse section and a latch section. The reference section includes a reference resistance and supplies a first...
6104211 System for preventing radiation failures in programmable logic devices  
A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can...
5731716 Programmable multibit register for coincidence and jump operations and coincidence fuse cell  
A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells...
5576633 Block specific spare circuit  
A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select...
5568061 Redundant line decoder master enable  
A master enable circuit is provided which receives multiple enable signal inputs while matching the redundant decoder enable delay with decoder enable delay. A master enable circuit contains a hard...
5543736 Gate array architecture and layout for deep space applications  
The present invention teaches an integrated circuit ("IC") gate array having improved reliability and increased immunity to deep space interference from electromagnetic radiation, photon energy,...
5396124 Circuit redundancy having a variable impedance circuit  
In a semiconductor memory having a redundant circuit, a plurality of first normal cells and a plurality of first spare cells are connected to a first pair of data lines, and a plurality of second...
5387823 Fuse-programmable redundancy control circuit  
A fuse-programmable control circuit has a master control circuit with a first fusible link that controls the feeding of power to a fuse-programmable memory. If output of signals from the...
5369314 Programmable logic device with redundant circuitry  
A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into...
5345110 Low-power fuse detect and latch circuit  
This invention is a low-power circuit for detecting and latching the state of a fusible link. During a power-up sequence, the circuit makes a one time determination regarding the blown or unblown...
5300840 Redundancy fuse reading circuit for integrated memory  
An integrated circuit memory comprising redundancy circuits with batteries of fuses to store the addresses of defective memory elements to be replaced by redundancy elements. The circuit used to...
5270976 Laser link decoder for DRAM redundancy scheme  
A decoder for a memory redundancy scheme is disclosed which allows replacement of a number of memory cell locations in connection with the state of a plurality of fuses.
5257229 Column redundancy architecture for a read/write memory  
An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The...
5175605 Single event upset hardening circuits, devices and methods  
The present invention provides a unique circuit and layout methods for improving upon series redundant circuits. A substitution device, comprising a pair of series connected N or P FETs for...
5117129 CMOS off chip driver for fault tolerant cold sparing  
A full swing CMOS logic circuit provides fault tolerant, cold sparing of VLSI logic devices attached to a high speed bus. P-channel FET transistors are formed in an N-well which has a biasing...
5047669 Tristate circuit using bipolar transistor and CMOS transistor  
In a semiconductor integrated circuit, drain-source paths of an NMOS transistor and a PMOS transistor are connected between the base and emitter of a bipolar transistor, and control signals are...
4922134 Testable redundancy decoder of an integrated semiconductor memory  
A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which...
4908525 Cut-only CMOS switch for discretionary connect and disconnect  
To provide for improving the yield in the manufacture of wafer-scale integrated (WSI) or restructurable very-large-scale integrated (RVLSI) CMOS circuitry, a low power switch circuit, fabricated...
4899067 Programmable logic devices with spare circuits for use in replacing defective circuits  
A programmable logic device having a plurality of word lines and a plurality of bit lines, each of which is programmably interconnectable to at least one of the word lines for producing on each bit...
4897563 N-way MMIC redundant switch  
An N-way redundant switch is implemented through the use of serial and parallel redundancy for providing redundancy in both ON and OFF operating modes.
4896055 Semiconductor integrated circuit technology for eliminating circuits or arrays having abnormal operating characteristics  
In a semiconductor integrated circuit, power lines or ground lines of a plurality of circuit blocks having equivalent functions are coupled via a switch circuit to a common main power line or main...
4791319 Semiconductor device with redundancy circuit and means for activating same  
A semiconductor device such as a DRAM with many signal line circuits is also provided with a redundancy circuit and is so structured that when one of the signal line circuits is defective and the...
4689494 Redundancy enable/disable circuit  
A redundancy enable/disable circuit for enabling and disabling subsequently the use of redundant elements includes first through third P-channel MOS transistors, an N-channel MOS transistor, an...
4641285 Line change-over circuit and semiconductor memory using the same  
The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal...
4614881 Integrated semiconductor circuit device for generating a switching control signal using a flip-flop circuit including CMOS FET's and flip-flop setting means  
An integrated semiconductor circuit device for generating a switching control signal includes a fuse having one terminal connected to a power source, and the other terminal connected to a flip-flop...
4613959 Zero power CMOS redundancy circuit  
A redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by...
4605872 Programmable CMOS circuit for use in connecting and disconnecting a semiconductor device in a redundant electrical circuit  
A programmable circuit is described which is particularly well suited for programming or customizing redundant elements in CMOS integrated circuits. This programmable circuit, which is formed on a...
4590388 CMOS spare decoder circuit  
A spare decoder provides for the substitution of a spare component for repair of a defective semiconductor chip. For example, a spare row or column of memory cells can be substituted for a...
4551815 Functionally redundant logic network architectures with logic selection means  
A programmable gate structure having functionally redundant architecture for enhanced production yields and reliability comprises a plurality of two-input nodes at least some of which may be...
4538247 Redundant rows in integrated circuit memories  
Decoding apparatus for an integrated circuit memory having normal rows of memory cells 10 and at least one selectively connectable redundant second row of memory cells 31 for being connected in...
4468735 Highly integrated programmable logic array utilizing AND and OR arrays  
A programmable logic array (PLA) is comprised of double-personalized cells conventionally arranged in an AND and OR array. In order to activate redundant or Don't Care positions, i.e., array...
4228528 Memory with redundant rows and columns  
A memory is provided with standard rows and columns and spare rows and columns for substitution for standard rows and columns found to have defective cells. Each of the decoders associated with a...
3800164 REDUNDANT LOGIC CIRCUIT  
This invention is directed to a redundant logic system having a plurality input channels and a single output channel. The system initially senses and compares the absolute magnitude of two of the...
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