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8803555 Apparatus and method for decoding an address in two stages  
Methods and apparatus for decoding of binary addresses and scanning rows and columns of an addressable array. In one example, an address decode circuit includes a first decoder circuit configured...
8797065 Selector circuit and processor system  
A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first...
8779799 Logic circuit  
A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is...
8610461 Split decode latch with shared feedback  
An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The...
8476932 Multiplex gate driving circuit  
A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the...
8373442 Selector circuit and processor system  
A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first...
8242808 Decoder circuit  
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a...
7969200 Decoder circuit  
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a...
7924606 Memory controller and decoder  
A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth...
7872504 Inverter and logic device comprising the same  
The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel...
7821299 Matrix decoder  
A matrix decoder is provided, which includes a plurality of first level shifters, a plurality of second level shifters, and a demultiplexer. The first level shifters and the second level shifters...
7821298 Multiplexing using product-of-sums and sum-of-products  
A method for and the results of implementing a tree of multiplexing are disclosed. At each level of the tree, a sum-of-products or a product-of-sums representation is chosen to maximize...
7795922 Decoder circuit  
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a...
7656197 Decoder circuit  
The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first...
7528631 Logic gate, scan driver and organic light emitting diode display using the same  
A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver...
7411424 Programmable logic function generator using non-volatile programmable memory switches  
Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power...
7203243 Line driver with reduced power consumption  
A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by...
7199618 Logic circuit arrangement  
A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a...
7129755 High-fanin static multiplexer  
An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each...
7088139 Low power tri-level decoder circuit  
A tri-level decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is configured to compare an input voltage to a first threshold, and the second...
7068069 Control circuit and reconfigurable logic block  
A control circuit for providing a control signal to build a logic circuit includes a latch circuit including first and second inverted logic gates; a first variable resistive memory provided...
7061275 Field programmable gate array  
A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure....
7049851 Decoder circuit  
A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first...
7042251 Multi-function differential logic gate  
A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop....
6998878 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit  
To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the...
6963227 Apparatus and method for precharging and discharging a domino circuit  
A domino circuit configuration includes a precharge transistor coupled to a discharge transistor, wherein the precharge transistor and the discharge transistor are not on simultaneously.
6954401 Semiconductor memory device integrating source-coupled-logic (SCL) circuit into an address buffer and a decoder  
It is an object of the invention to provide a circuit configuration wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signal Φ1 and the decoder control...
6943589 Combination multiplexer and tristate driver circuit  
A combination multiplexer and tristate circuit. A multiplexer circuit may be configured to receive at least a first data input and a second data input, which are selected by at least a first...
6924670 Complementary input dynamic muxed-decoder  
A muxed-decoder circuit including multiple complementary input dynamic circuits and an AND logic gate. Each complementary input dynamic circuit includes a complementary P-logic AND dynamic...
6859412 Circuit for controlling driver strengths of data and data strobe in semiconductor device  
A circuit for controlling driver strengths of a data and a data strobe in a semiconductor device comprising: a control signal generating unit which generates a first control signal in response to...
6794906 Decoder scheme for making large size decoder  
An improved multi-stage binary hierarchy decoder characterized in that at least one of the decoding stages subsequent to the first stage is implemented as a Transmission Gate Matrix (TGM) in which...
6756820 Optimized-delay multiplexer  
The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted...
6696864 Logic circuit and its forming method  
This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the...
6657459 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them  
A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough...
6646949 Word line driver for dynamic random access memories  
A word line for a row of memory elements of a dynamic random access memory. A first transistor is connected to a source of negative potential and to the word line for switching the word line to a...
6624665 CMOS skewed static logic and method of synthesis  
A new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit. The skewed gate uses a plurality of transistors matched and joined...
6618316 Pseudo-static single-ended cache cell  
A cache memory cell comprising a read-access transistor to access the cell, where the read-access transistor is reverse biased when the memory cell is not being read to reduce sub-threshold...
6593776 Method and apparatus for low power domino decoding  
A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple...
6586970 Address decoder with pseudo and or pseudo nand gate  
The present invention describes a multi-stage decoder and method of decoding utilizing a pseudo NAND or pseudo AND gate in one of the stages. This invention presents a decoder comprising a first...
6552575 Word line testability improvement  
The present invention proposes a method of disabling a particular decoder output during scan-mode testing without impacting the critical path during either scan-mode or the normal mode of...
6552566 Logic array circuits using silicon-on-insulator logic  
Logic array circuits are formed on SOI substrates. The pull-down network (130) of the logic array circuit comprises NMOS transistors (125) and PMOS transistors (120) configured in series.
6518792 Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling  
A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit...
6476644 Clocked logic gate circuit  
A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one...
6459303 High speed programmable address decoder  
A high-performance address decoder circuit provides higher speed read and write access for an embedded memory of a programmable logic integrated circuit. The address decoder is programmable to...
6426655 Row decoder with switched power supply  
A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for...
6404237 Boosted multiplexer transmission gate  
An apparatus and method for boosting a transmission gate by charging a pair of capacitors and using the coupling effect of that pair of capacitors to overdrive the gate inputs of NMOS and PMOS...
6396306 Regenerative tie-high tie-low cell  
A regenerative tie-high, tie-low cell (circuit) that provides unconditionally stable logic (1 and 0) output states used to tie off logic inputs. The circuit of this invention eliminates any...
6392445 Decoder element for producing an output signal having three different potentials  
The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The...
6388472 Word line decoder  
A word line decoder is characterized in that addresses for decoding word lines are divided into a global word line and a local word line, and if said global word line is selected, a voltage...
6362658 Decoder for memories having optimized configuration  
A decoder with reduced complexity includes at least one OR circuit section and at least one AND circuit section. The at least one OR circuit section may include first and second circuit lines...

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