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7602216 Integrated circuit device and electronic instrument  
An integrated circuit device includes a first predriver that drives an N-type power MOS transistor of an external driver including the N-type power MOS transistor and a P-type power MOS transistor,...
7589566 Semiconductor device provided with antenna ratio countermeasure circuit  
A CMOS LSI includes an inverter including first and second MOS transistors, a relatively long metal interconnection connected to an input node of the inverter, first and second diodes releasing...
7579866 Programmable logic device with configurable override of region-wide signals  
A programmable logic device architecture providing efficient configurable functionality to allow the “tie-off” of logic region-wide control signals. This functionality is provided while...
7568177 System and method for power gating of an integrated circuit  
Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is...
7554358 Programmable logic devices with user non-volatile memory  
Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention,...
7548095 Isolation scheme for static and dynamic FPGA partial programming  
An isolation scheme to permit partial programming of FPGA integrated circuits controlled by Flash memory cells includes a p-type semiconductor region. First and second spaced apart deep n-wells are...
7545168 Clock tree network in a field programmable gate array  
A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a...
7538580 Logic array devices having complex macro-cell architecture and methods facilitating use of same  
Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate...
7536666 Integrated circuit and method of routing a clock signal in an integrated circuit  
The various embodiments of the present invention relate to coupling clock signals between a plurality of data transceivers. According to one embodiment, a clock routing circuit having data...
7535255 Logic integrated circuit having dynamic substitution function, information processing apparatus using the same, and dynamic substitution method of logic integrated circuit  
A logic integrated circuit reconfigures a reconfigurable circuit to a circuit having the function of a fixed circuit at the time of a fault in the fixed circuit. The fixed circuits are divided into...
7521962 Semiconductor integrated circuit apparatus  
A semiconductor integrated circuit apparatus relates to a structured ASIC that wires functional cells in a common wiring layer, which is not dependent on a user circuit and common to several sorts,...
7518409 Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same  
An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively...
7511536 Cells of a customizable logic array device having independently accessible circuit elements  
Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a...
7477073 Structures and methods for heterogeneous low power programmable logic device  
A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where...
7474125 Method of producing and operating a low power junction field effect transistor  
A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said...
7468614 Configurable integrated circuit with offset connections  
Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC...
7447828 Programmable crossbar signal processor used as morphware  
A method includes providing a crossbar array including a programmable material layer, wherein the crossbar array is configured to function as part of a signal processing system and reprogramming at...
7439767 Semiconductor integrated circuit and construction using densely integrated cells  
A semiconductor integrated circuit having a first cell row including a plurality of cells disposed in a row direction, each cell having a prescribed cell width in the row direction and at least one...
7432732 Integrated circuit device including interface circuit and electronic apparatus  
An integrated circuit device, includes: an input pad region including a differential signal input region receiving a pair of differential signals, a first power supply input region and a second...
7423453 Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric  
Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of...
7420392 Programmable gate array and embedded circuitry initialization and processing  
Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions...
7414437 Nanomechanical computer  
An electromechanical switching device employs a first nanoscale pillar shuttling charge between opposed charged electrodes. Motion of the first pillar is coupled to a second set of pillars...
7409659 System and method for suppressing crosstalk glitch in digital circuits  
A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk...
7388401 Input/output circuit device  
An input/output circuit device includes a first transistor which is formed at a substrate, a first gate of which receives an input signal, one of a first source and drain of which is connected to a...
7382157 Interconnect driver circuits for dynamic logic  
Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or...
7378874 Creating high-drive logic devices from standard gates with minimal use of custom masks  
Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized...
7378871 Programmable device with structure for storing configuration information  
In a programmable cell included in a first region, configuration information is stored in a volatile memory, while in a programmable cell included in a second region, configuration information is...
7375548 SCL type FPGA with multi-threshold transistors and method for forming same  
A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering...
7372298 Chip with adjustable pinout function and method thereof  
A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a...
7368943 Enhanced scheme to implement an interconnection fabric using switching networks in hierarchy  
An interconnection fabric using switching networks organized in multiple levels of hierarchy to allow flexible interconnections of the switching networks amongst different levels of hierarchy and...
7365568 Method and circuit for reducing programmable logic pin counts for large scale logic  
A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger...
7353481 Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit  
A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a...
7352208 Integrated circuit having a plurality of output drivers  
One embodiment of the invention provides an integrated circuit having a plurality of output drivers for driving signals from the integrated circuit and having a plurality of supply terminals to...
7339400 Interface port for electrically programmed fuses in a programmable logic device  
A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that...
7334206 Cell builder for different layer stacks  
A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of...
7312633 Programmable routing structures providing shorter timing delays for input/output signals  
Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to...
7312631 Structures and methods for avoiding hold time violations in a programmable logic device  
Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the...
7305647 Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage  
A semiconductor design layout having a deep well structure for routing body-bias voltage is generated using standard pattern tiles and custom pattern tiles. These tiles have a tile shape and a tile...
7304498 Clock circuitry for programmable logic devices  
Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which...
7304497 Methods and apparatus for programmably powering down structured application-specific integrated circuits  
Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that...
7304496 Mask-programmable logic device with programmable input/output ports  
A mask-programmable logic device includes a macrocell having an external input/output port for “place-and-route” programming by addition of metallization layers. A programmable “fixed”...
7302513 Programmable crossbar signal processor  
A signal processing system is taught to be formed by combining a crossbar array with programming circuitry and signal input circuitry so as to provide a linear transformation from a set of input...
7301363 Method and system for improving communication between logic elements in an integrated circuit  
A method, apparatus and machine-readable medium for improving communication between logic elements in an integrated circuit (IC) is provided. This is achieved by using a point-to-point approach for...
7292063 Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an I/O region  
A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC)...
7292062 Distribution of signals throughout a spine of an integrated circuit  
A system and method for distributing signals throughout an integrated circuit (IC). The system comprises a transmitter unit and a plurality of receiver units. The transmitter unit combines a...
7285974 Large scale integrated circuit  
An large scale integrated circuit (LSI) includes an input buffer for adjusting a signal input to an outer input terminal; an input side selector for outputting the signal to a first output side...
7274214 Efficient tile layout for a programmable logic device  
In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and at least one column of routing multiplexers driving interconnect lines that can be used...
7274207 Semiconductor-integrated circuit utilizing magnetoresistive effect elements  
A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects...
7253662 Method for forming an electric device comprising power switches around a logic circuit and related apparatus  
A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic...
7209987 Embedded system design through simplified add-on card configuration  
Provided are a method and a system for designing an embedded system using a design process for building a general-purpose computer. Specifically, the embedded system design includes adding and...
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