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8174996 Adaptive test system for network function and performance evaluation  
A method may include receiving a first set of parameters associated with a test environment, the test environment including a test system for testing a network, receiving a test objective,...
8174284 Repairable IO in an integrated circuit  
Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) are disclosed. One embodiment of the present invention includes repairable IO circuitry...
8067954 Fault tolerant integrated circuit architecture  
The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of...
8013627 Semiconductor device and method of fabricating the same  
Provided is a semiconductor device and a method of fabricating the same. The semiconductor device may include at least one logic circuit and at least one spare circuit. The at least one spare...
7999567 SEU tolerant arbiter  
Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter...
7948260 Method and apparatus for aligning the phases of digital clock signals  
A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a...
7906984 Relocatable field programmable gate array bitstreams for fault tolerance  
A Field Programmable Gate Array (FPGA) circuit capable of operating through at least one fault. The FPGA circuit includes a configuration memory and an embedded microprocessor. The embedded...
7902855 Repairable IO in an integrated circuit  
Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) arc disclosed. One embodiment of the present invention includes repairable IO circuitry...
7898284 Asynchronous nano-electronics  
Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a...
7852107 Single event upset mitigation  
In one embodiment of the invention, a method is provided for protecting against single event upsets of a circuit in programmable logic. Configuration memory cells of the programmable logic are...
7812629 Resilient integrated circuit architecture  
The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of...
7772872 Multi-row block supporting row level redundancy in a PLD  
In a Programmable Logic Device (PLD), a multi-row block that has internal logic connections between rows has redundant internal connections between rows to replace the internal logic connections...
7755408 Redundancy in signal distribution trees  
A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by...
7750676 Embedded system and control method therefor  
An embedded system having a programmable logic circuit, a plurality of storage devices each storing configuration data defining circuit information of the logic circuit, a setting information...
7746100 Flexible adder circuits with fast carry chain circuitry  
Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a...
7661047 Method and dual interlocked storage cell latch for implementing enhanced testability  
A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch...
7646209 Semiconductor integrated circuit and method of production of same  
A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal...
7642813 Error correcting logic system  
The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an...
7644327 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA  
A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide...
7619438 Methods of enabling the use of a defective programmable device  
Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying...
7616024 Resilient integrated circuit architecture  
The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of...
7612577 Speedpath repair in an integrated circuit  
A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also...
7609083 Semiconductor integrated circuit device and storage apparatus having the same  
A semiconductor integrated circuit device includes: a first large scale integrated circuit including a plurality of first logical blocks; a programmable second large scale integrated circuit...
7598765 Redundant configuration memory systems and methods  
Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable...
7589552 Integrated circuit with redundancy  
Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks...
7564259 Digital circuit with dynamic power and performance control via per-block selectable operating voltage  
A digital circuit with dynamic power and performance control via per-block selectable operating voltage level permits dynamic tailoring of operating power to processing demand and/or compensation...
7550992 Logic cell with two isolated redundant outputs, and corresponding integrated circuit  
The disclosure relates to a logic cell for an integrated circuit, including two redundant outputs, a first output equipped with an output transistor of type P and a second output equipped with an...
7548084 Fault tolerant integrated circuit architecture  
The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of...
7545688 Semiconductor device  
There is provided a semiconductor device including: plural macros each having plural normal blocks and a redundant block to be used as a replacement for a normal block; a first replacement...
7523422 Method of fabricating an integrated circuit to improve soft error performance  
The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by...
7508231 Programmable logic device having redundancy with logic element granularity  
A PLD having logic element row granularity redundancy is disclosed. The PLD includes a plurality of LABs arranged in an array and a plurality of horizontal and vertical inter-LAB lines...
7504850 Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit  
Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each...
7477091 Defect tolerant redundancy  
Circuits, methods, and apparatus for using redundant circuitry on integrated circuits in order to increase manufacturing yields. One exemplary embodiment of the present invention provides a circuit...
7457187 Design structure for in-system redundant array repair in integrated circuits  
A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control...
7423448 Radiation hardened logic circuit  
A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an...
7411412 Semiconductor integrated circuit  
A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection...
7411411 Methods and systems for hardening a clocked latch against single event effects  
Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a...
7408380 Method and apparatus for a redundant transceiver architecture  
A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model...
7405990 Method and apparatus for in-system redundant array repair on integrated circuits  
Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays....
7345506 Redundancy method and software to provide improved interconnect efficiency for programmable logic devices  
A method and computer readable medium for implementing redundancy on a programmable logic device with improved interconnect efficiency. The method and medium includes: determining if a first wire...
7336115 Redundancy in signal distribution trees  
A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by...
7301362 Duplicated double checking production rule set for fault-tolerant electronics  
Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to...
7298168 Method and apparatus for error mitigation of programmable logic device configuration memory  
A method and apparatus to reduce the probability of programmable logic device (PLD) failure due to single event upset (SEU) of configuration memory. A first portion of configuration memory cells...
7292060 Logic circuit and method thereof  
An example embodiment of the present invention relates to a method of executing a logic operation while remaining safe from side channel attacks. Another example embodiment of the present invention...
7286020 Techniques for monitoring and replacing circuits to maintain high performance  
Techniques are provided for monitoring the performance of circuits and replacing low performing circuits with higher performing circuits. A frequency detector compares the frequency of a first...
7276931 System and method for creating replacements for obsolete computer chips  
A system and method for replacing a malfunctioning logic device with a substitute logic device. The system provides a replacement assembly that contains a complex programmable logic device, a...
7277346 Method and system for hard failure repairs in the field  
A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit...
7265573 Methods and structures for protecting programming data for a programmable logic device  
Methods and structures for protecting programmable logic device (“PLD”) programming files are disclosed. In one respect, an embodiment of the present invention includes applying a particular pro...
7266721 Runtime repairable processor  
A self repairable processor that provides a reliable computing result without increasing the footprint of the on-chip devices. The processor has a plurality of data registers connected to two...
7215581 Triple redundant latch design with low delay time  
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each...
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