|
Match
|
Document |
Document Title |
|
|
7512033 |
Apparatus and method for controlling clock signal in semiconductor memory device
An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation...
|
|
|
7352826 |
Analog delay circuit
An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the...
|
|
|
7103274 |
Cross-connect apparatus
An apparatus having n-number of working cross-connects for cross-connecting an n-bit input signals arriving from a plurality of input paths on a per-bit basis; n-number of first logic circuits for...
|
|
|
7020794 |
Interleaved delay line for phase locked and delay locked loops
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and...
|
|
|
7015600 |
Pulse generator circuit and semiconductor device including same
A pulse generator circuit is disclosed including a delay element coupled to a logic circuit. The delay element receives a clock signal CLK and a signal X and produces a signal XN dependent upon the...
|
|
|
6889349 |
Digital event sampling circuit and method
A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second...
|
|
|
6091165 |
Method and apparatus to reduce peak electro-magnetic emissions from ground and power planes
A method and an apparatus reduce peak electro-magnetic (EM) emissions from power and ground planes in, for example, a printed circuit board (PCB) by phase shifting synchronous signal sources to...
|
|
|
5537655 |
Synchronized fault tolerant reset
A synchronizing circuit comprises a plurality of substantially identical modules for receiving respective asynchronous input signals and respective local clock signals with the local clock signals...
|
|
|
5465347 |
System for reducing phase difference between clock signals of integrated circuit chips by comparing clock signal from one chip to clock signal from another chip
A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal...
|
|
|
5440592 |
Method and apparatus for measuring frequency and high/low time of a digital signal
A delay chain having a known number of delay elements providing various delayed outputs of its input, a first and a second register set, and preferably, an array of multiplexors, are provided to...
|
|
|
5428764 |
System for radial clock distribution and skew regulation for synchronous clocking of components of a computing system
A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency,...
|
|
|
5369640 |
Method and apparatus for clock skew reduction through remote delay regulation
A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a...
|
|
|
5347184 |
Dual receiver edge-triggered digital signal level detection system
Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and...
|
|
|
5184210 |
Structure for controlling impedance and cross-talk in a printed circuit substrate
An arrangement for interconnecting high density signals of integrated circuits includes an electronic circuit on a multilayered substrate which includes at least three layers. These layers comprise...
|
|
|
5078464 |
Optical logic device
An optical logic device based on the time-shift-keying architecture is described in which digital logic functions are realized by applying appropriate signal pulses to a nonlinear shift or "chirp"...
|
|
|
5070787 |
Method and apparatus for switching an electrical circuit
The invention provides an explosively actuated switch and a method of using the same. The switch will include primary conductive elements which will remain generally stationary, and one or more...
|
|
|
5024499 |
Optical and gate for use in a cross-bar arithmetic/logic unit
An optical AND gate for use in a cross-bar arithmetic/logic unit including first and second optical substrates which are configured adjacent to one another with each of the optical substrates...
|
|
|
4973122 |
Optical nonlinear cross-coupled interferometer and method utilizing same
An optical device includes a 50-50 cross-coupler having a pair of ports optically coupled by a waveguide which includes a portion of material having a non-linear refractive index with a relaxation...
|
|
|
4964687 |
Optical latch and method of latching data using same
An optical latch includes first and second optical switches arranged in series. An input signal is received in the first optical switch and is passed through to the second optical switch. The...
|
|
|
4961621 |
Optical parallel-to-serial converter
An optical parallel-to-serial converter constructed from at least two optical shift registers coupled in cascade by an optical two-to-one combiner. The input port of the first optical shift...
|
|
|
4923267 |
Optical fiber shift register
An optical shift register constructed from at least two optical memory cells connected in cascade, each memory cell having an optical combiner, a 1×2 optical switch, a clock, and an optical...
|
|
|
4877974 |
Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency
A clock generator which is cascade connected a plurality of single-phase pulse generator circuits including RS flip-flops and delay circuits for defining the pulse width of one output at the RS...
|
|
|
4713621 |
Phase synchronization circuit
A phase synchronization circuit for controlling a graphic display device in a teletext receiving system. The phase synchronization circuit includes a delay circuit, adapted to delay in sequence...
|
|
|
4463440 |
System clock generator in integrated circuit
A system clock generator for use in a CMOS LSI chip includes a clock control signal generator for developing a control signal in response to a clock generating instruction or inhibition...
|
|
|
4390801 |
Circuit for reproducing a clock signal
A circuit for reproducing a clock signal from digital signals reproduced from a recording medium makes self-clocking possible. The circuit includes a phase lock loop having a voltage-controlled...
|
|
|
3524991 |
STATIC ELEMENTS HAVING LOGICAL FUNCTIONS
|
|
|
3390277 |
Logical devices
|
|
|
3303351 |
Logical circuit using magnetic cores
|
|
|
3271581 |
Magnetic nor device
|
|
|
3264488 |
Balanced current pumped parametric converter
|
|
|
3264487 |
Magnetic logic circuit
|
|
|
3241129 |
Delay line
|
|
|
3233113 |
Clock generator
|
|
|
3231753 |
Core memory drive circuit
|
|
|
3213289 |
Inhibit logic means
|
|
|
3197719 |
Impedance matching source to line for pulse frequencies without attenuating zero frequency
|
|
|
3193692 |
Magnetic thin film amplifier
|
|
|
3177378 |
Transistor amplifier and frequency multiplier
|
|
|
3175184 |
Static logic power control
|
|
|
3169195 |
Magnetic delay circuits for computer systems
|
|
|
3157794 |
Magnetic core logical circuits
|
|
|
3119023 |
Magnetic circuits
|
|
|
3118070 |
Electrical control circuits
|
|
|
3117234 |
Time delay circuits
|
|
|
3109935 |
Resonant logic circuits employing tunnel diodes
|
|
|
3104333 |
Low frequency oscillator utilizing saturable magnetic timing core
|
|
|
3104325 |
Binary trigger
|
|
|
3103649 |
Asynchronous to synchronous converter for use in data processing apparatus
|
|
|
3097306 |
Magnetic core digital storage and transfer circuits
|
|
|
3093747 |
Magnetic signal storage logic computing element
|