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7435652 Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET  
Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal...
7432164 Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same  
A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity...
7416949 Fabrication of transistors with a fully silicided gate electrode and channel strain  
Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer...
7384830 Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates  
A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate...
7382023 Fully depleted SOI multiple threshold voltage application  
An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a...
7368372 Methods of fabricating multiple sets of field effect transistors  
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a...
7361960 Semiconductor device and method of manufacturing the same  
A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from...
7355281 Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode  
A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After...
7355256 MOS Devices with different gate lengths and different gate polysilicon grain sizes  
A semiconductor device 1 according to the present invention includes a semiconductor substrate 5 , a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first...
7354816 Field effect transistor with gate spacer structure and low-resistance channel coupling  
Spacer structures of field effect transistor structures are enhanced at least in sections with immobile charge carriers. The charge accumulated in the spacer structures induces an enhancement zone...
7341916 Self-aligned nanometer-level transistor defined without lithography  
A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in...
7341900 Semiconductor device and method for manufacturing the same  
A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit...
7339240 Dual-gate integrated circuit semiconductor device  
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a...
7338860 Methods of forming non-volatile memory device having floating gate  
Embodiments of the present invention are directed to methods for forming non-volatile memory devices. A substrate is provided that has a cell region, a first peripheral region, and second...
7332420 Method for manufacturing semiconductor device  
A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a...
7326631 Method of manufacturing MOS transistors with gate electrodes formed in a packet of metal layers deposited upon one another  
Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one...
7312126 Process for producing a layer arrangement, and layer arrangement for use as a dual gate field-effect transistor  
The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate, a first semiconductor layer is...
7312124 Method of manufacturing a semiconductor device  
A method of manufacturing a semiconductor device includes forming first and second active regions and a field region in a surface of a substrate; forming a first gate insulating film in the first...
7306996 Methods of fabricating a semiconductor device having a metal gate pattern  
A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern...
7306990 Information storage element, manufacturing method thereof, and memory array  
An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity ( 6 ), and a floating gate...
7282403 Temperature stable metal nitride gate electrode  
An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate...
7268064 Method of forming polysilicon layer in semiconductor device  
Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to...
7265423 Technique for fabricating logic elements using multiple gate layers  
Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific...
7262447 Metal oxide silicon transistor and semiconductor apparatus having high λ and β performances  
A semiconductor apparatus includes a MOS transistor having a semiconductor substrate providing as a channel region between a source and a drain. A gate electrode is formed on the semiconductor...
7259070 Semiconductor devices and methods for fabricating the same  
Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a...
7256125 Method of manufacturing a semiconductor device  
For improving the reliability of a semiconductor device having a stacked structure of a polycrystalline silicon film and a tungsten silicide film, the device is manufactured by forming a...
7256078 High mobility plane FinFETs with equal drive strength  
An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second...
7229873 Process for manufacturing dual work function metal gates in a microelectronics device  
The present invention provides a method of forming a dual work function metal gate microelectronics device 200 . In one aspect, the method includes forming nMOS and pMOS stacked gate structures ...
7211872 Device having recessed spacers for improved salicide resistance on polysilicon gates  
A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed...
7205619 Method of producing semiconductor device and semiconductor device  
A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit...
7193253 Transition metal alloys for use as a gate electrode and devices incorporating these alloys  
Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or...
7183168 Method of manufacturing a semiconductor device having a silicide film  
A method of manufacturing a semiconductor device includes implanting germanium ions into a selected portion of a semiconductor region containing at least silicon, forming P-type and N-type...
7172955 Silicon composition in CMOS gates  
A semiconductor device comprises an n-type MIS transistor comprising a first gate insulating film and a first gate electrode including an MSi x film formed on the first gate insulating film, where...
7157378 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode  
A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate...
7153784 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode  
A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After...
7148096 Method of manufacturing a semiconductor device having a gate electrode containing polycrystalline silicon-germanium  
An aspect of the present invention includes a first conductive type semiconductor region formed in a semiconductor substrate, a gate electrode formed on the first conductive type semiconductor...
7145207 Gate structure of semiconductor memory device  
A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of...
7138305 Method and apparatus for improving stability of a 6T CMOS SRAM cell  
The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device...
7129580 Methods and procedures for engineering of composite conductive films by atomic layer deposition  
A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides...
7118963 Semiconductor memory integrated circuit and its manufacturing method  
A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film ( 21 a...
7112857 Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations  
An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating...
7091077 Method of directionally trimming polysilicon width  
Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer....
7087492 Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate  
A gate electrode layer is doped in a first section of a semiconductor substrate. By means of a patterning, encapsulated gate electrodes emerge from the gate electrode layer, which gate electrodes...
7084035 Semiconductor device placing high, medium, and low voltage transistors on the same substrate  
A method for forming three kinds of MOS transistors on a single semiconductor substrate, each provided with gate oxides different in thickness from each other, without detracting from the device...
7067378 Methods of fabricating multiple sets of field effect transistors  
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a...
7067370 Method of manufacturing a MOS transistor of a semiconductor device  
A method of manufacturing a transistor of a semiconductor device is provided. The method includes forming an N type gate pattern and a P type gate pattern on a substrate, implanting N type...
7060570 Methods of fabricating multiple sets of field effect transistors  
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a...
7060569 Methods of fabricating multiple sets of field effect transistors  
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a...
7052945 Short-channel Schottky-barrier MOSFET device and manufacturing method  
A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device...
7049242 Post high voltage gate dielectric pattern plasma surface treatment  
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a...
Matches 1 - 50 out of 159 1 2 3 4 >