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7402886 Memory with self-aligned trenches for narrow gap isolation regions  
Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region...
7402885 LOCOS on SOI and HOT semiconductor device and method for manufacturing  
One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other...
7393730 Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same  
In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator...
7385275 Shallow trench isolation method for shielding trapped charge in a semiconductor device  
A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow...
7384869 Protection of silicon from phosphoric acid using thick chemical oxide  
A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide...
7384836 Integrated circuit transistor insulating region fabrication method  
A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate...
7358145 Method of fabricating shallow trench isolation structure  
A method of fabricating a shallow trench isolation structure is provided. A substrate is provided with a pad layer, a mask layer and a shallow trench formed therein. A liner oxide layer is formed...
7348639 Method for providing a deep connection to substrate or buried layer in a semiconductor device  
A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial...
7348254 Method of fabricating fin field-effect transistors  
A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an...
7344954 Method of manufacturing a capacitor deep trench and of etching a deep trench opening  
A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a...
7342272 Flash memory with recessed floating gate  
A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of...
7335568 Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same  
In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk...
7327014 Semiconductor integrated circuit device and process for manufacturing the same  
A large area dummy pattern DL is formed in a layer underneath a target T 2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy...
7327009 Selective nitride liner formation for shallow trench isolation  
A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a...
7326625 Trench structure having a void and inductor including the trench structure  
In a method of forming a trench structure having a wide void therein, a first trench having a first width and a first depth is formed in a substrate. The first trench is filled with a first...
7323739 Semiconductor device having recess and planarized layers  
A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically...
7307002 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication  
A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount...
7303964 Self-aligned STI SONOS  
Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a...
7297608 Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition  
A method employing atomic layer deposition rapid vapor deposition (RVD) conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film is then...
7294573 Method for controlling poly 1 thickness and uniformity in a memory array fabrication process  
According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon...
7294556 Method of forming trench isolation in the fabrication of integrated circuitry  
This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one...
7288452 Method for manufacturing semiconductor device  
A method of manufacturing a semiconductor device including forming an ONO film on a semiconductor substrate and a hard mask layer on the ONO film, forming a trench by etching the hard mask layer...
7279396 Methods of forming trench isolation regions with nitride liner  
The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one...
7273793 Methods of filling gaps using high density plasma chemical vapor deposition  
The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber....
7268043 Semiconductor device and method of manufacturing the same  
A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the...
7265420 Semiconductor substrate layer configured for inducement of compressive or expansive force  
An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate...
7265017 Method for manufacturing partial SOI substrates  
There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate...
7262111 Method for providing a deep connection to a substrate or buried layer in a semiconductor device  
A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial...
7259073 Semiconductor device and method of manufacturing the same  
A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench...
7259069 Semiconductor device and method of manufacturing the same  
A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the...
7247922 Inductor energy loss reduction techniques  
An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current...
7244991 Semiconductor integrated device  
A semiconductor integrated apparatus, including: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating...
7244658 Low stress STI films and methods  
The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine...
7242012 Lithography device for semiconductor circuit pattern generator  
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and...
7235460 Method of forming active and isolation areas with split active patterning  
A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in...
7224035 Apparatus and fabrication methods for incorporating sub-millimeter, high-resistivity mechanical components with low-resistivity conductors while maintaining electrical isolation therebetween  
Fabricating electrical isolation properties into a MEMS device is described. One embodiment comprises a main substrate layer of a high-resistivity semiconductor material, such as high-resistivity...
7223696 Methods for maskless lithography  
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and...
7221035 Semiconductor structure avoiding poly stringer formation  
The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a...
7217633 Methods for fabricating an STI film of a semiconductor device  
Methods for fabricating a shallow trench isolation (STI) of a semiconductor device are disclosed. A disclosed method includes: forming a trench on a semiconductor substrate, forming an oxide layer...
7211497 Method for fabricating semiconductor devices  
According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on...
7208812 Semiconductor device having STI without divot and its manufacture  
The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride...
7205190 Semiconductor device fabrication method  
The present invention adequately activates a substrate contact region of a support substrate without substantially changing the conventional SOI-CMOS device formation process. An exposed face of...
7196396 Semiconductor device having STI without divot and its manufacture  
The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride...
7192816 Self-aligned body tie for a partially depleted SOI device structure  
A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias...
7176549 Shallow trench isolation using low dielectric constant insulator  
A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during...
7176545 Apparatus and methods for maskless pattern generation  
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and...
7176101 Method of forming isolation oxide layer in semiconductor integrated circuit device  
A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming...
7160786 Silicon on insulator device and layout method of the same  
A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a...
7154164 Semiconductor integrated circuit device and process for manufacturing the same  
A large area dummy pattern DL is formed in a layer underneath a target T 2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy...
7154159 Trench isolation structure and method of forming the same  
A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the...
Matches 1 - 50 out of 284 1 2 3 4 5 6 >