Matches 401 - 450 out of 497 < 1 2 3 4 5 6 7 8 9 10 >
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4441931 Method of making self-aligned guard regions for semiconductor device elements  
A method for forming a guard zone (21) is disclosed, suitable for a guard ring for a Schottky barrier diode or for a channel guard zone for protecting the channel inversion layer of an insulated...
4435895 Process for forming complementary integrated circuit devices  
A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The...
4434036 Method and apparatus for doping semiconductor material  
Method for doping semiconductor material, including a container into which doping material is led and aimed at the semiconductor material by means of an electrical field, which includes maintaining...
4418469 Method of simultaneously forming buried resistors and bipolar transistors by ion implantation  
A method of making at a relatively low temperature, a resistor region of a high sheet resistance, solely or together with other circuit devices such as bipolar transistors in an IC chip, with the...
4415372 Method of making transistors by ion implantations, electron beam irradiation and thermal annealing  
The invention provides a method for fabricating a semiconductor device which comprises the steps of ion-implanting an impurity into a monocrystalline semiconductor substrate; irradiating the region...
4412376 Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation  
A vertical PNP bipolar transistor structure with Schottky Barrier diode emitter is disclosed which simplifies the structure and process steps for combining a complementary PNP in an NPN integrated...
4393577 Semiconductor devices and method of manufacturing the same  
In a semiconductor device of the type comprising a semiconductor substrate made of P type silicon, a P type monocrystalline silicon region formed on the major surface of the substrate and...
4386968 Method of making semiconductor device structures by means of ion implantation under a partial pressure of oxygen  
Disclosed is a simplified method of producing semiconductor device structures in an integrated technology using at least one ion implantation step. Implantation of the doping ions into a silicon...
4385433 Method of forming metal silicide interconnection electrodes in I.sup.2 L-semiconductor devices  
An exposed surface of a semiconductor substrate with an integrated injection logic semiconductor region having a first conductivity injector region of which one surface is exposed, a first...
4381952 Method for fabricating a low loss varactor diode  
A low conductivity, first conductivity type epitaxial layer is formed on a substrate of high conductivity, first conductivity type semiconductor material. Conductivity modifiers of second...
4373252 Method for manufacturing a semiconductor structure having reduced lateral spacing between buried regions  
The lateral spacing between buried regions separated by oxide-isolation regions in a semiconductor structure is reduced to as little as one micron by performing a deep implantation of ions of the...
4370176 Process for fast droping of semiconductors  
The present invention relates to a process for fast doping of semiconductors, consisting in implanting foreign particles in a substrate and in rendering them electrically active so as to modify the...
4362574 Integrated circuit and manufacturing method  
A method used to form a field effect device and a bipolar device in different regions of the same semiconductor material, such method including the step of forming a doped layer in the...
4354307 Method for mass producing miniature field effect transistors in high density LSI/VLSI chips  
In the disclosed method, dopant atoms of a first conductivity type are implanted into the surface of a semiconductor substrate to form a channel region of each transistor having a relatively high...
4350537 Semiconductor annealing by pulsed heating  
A process for annealing crystal damage in ion implanted semiconductor devices in which the device is rapidly heated to a temperature between 450° and 900° C. and allowed to cool. It has been...
4332627 Method of eliminating lattice defects in a semiconductor device  
The invention relates to a semiconductor device and to a method of fully eliminating lattice defects in N-conductive zones of a semiconductor device which are generated by ion implantation of...
4315781 Method of controlling MOSFET threshold voltage with self-aligned channel stop  
A process is provided for fabricating MOSFET devices having field source, gate and drain regions. The threshold voltage of both the channel and field regions of such devices is controlled by...
4298401 Breakdown voltage resistor obtained through a double ion-implantation into a semiconductor substrate, and manufacturing process of the same  
An implanted resistor structure for semiconductor integrated circuit devices is formed by a double ion-implantation providing a high breakdown voltage resistor.
4295264 Method of making integrated circuit MOS capacitor using implanted region to change threshold  
An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. The lower plate consists of a region which is...
4295898 Method of making isolated semiconductor devices utilizing ion-implantation of aluminum and heat treating  
In forming p + -type isolation region to define an isolated n-type island region in an n-type epitaxial layer grown on a p-type semiconductor substrate, the p + -type isolation region is formed...
4278476 Method of making ion implanted reverse-conducting thyristor  
A method for making a pnpn semiconductor reverse conducting thyristor comprises the steps of forming n-type semiconductor layers on both sides of a p-type semiconductor substrate for forming an...
4276095 Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations  
A MOSFET device structure is disclosed where the channel region has formed therein a buried layer of dopant of the same conductivity type as the source and drain, so that the depletion layers for...
4261763 Fabrication of integrated circuits employing only ion implantation for all dopant layers  
This disclosure relates to a method of fabricating an integrated circuit wherein all dopant layers are formed by ion implantation. More specifically, the buried collector of a bipolar integrated...
4247343 Method of making semiconductor integrated circuits  
The proposed method of making semiconductor integrated circuits comprises sequential formation on a p-substrate of a first layer of n-regions, an epitaxial p-layer, a second layer of n-regions with...
4247862 Ionization resistant MOS structure  
A structure and method for preventing minority carriers caused by an alpha particle, or the like, from drifting into storage regions and causing a false data bit. In a high density MOS circuit, a...
4243433 Forming controlled inset regions by ion implantation and laser bombardment  
A semiconductor integrated circuit structure in which the inset regions are ion implanted and laser annealed to maintain substantially the dimensions of the implantation and the method of forming...
4240843 Forming self-guarded p-n junctions by epitaxial regrowth of amorphous regions using selective radiation annealing  
The specification describes structures, and methods for making them, in which self-guarded p-n junctions or the electrical isolation between multiple devices in an integrated circuit are formed...
4230505 Method of making an impatt diode utilizing a combination of epitaxial deposition, ion implantation and substrate removal  
A method of making an Impatt diode capable of operating at millimeter wave frequencies in which an epitaxial layer of the thickness desired for the diode is deposited on a substrate. Conductivity...
4218267 Microelectronic fabrication method minimizing threshold voltage variation  
A microelectronic fabrication process for minimizing the threshold voltage variation across the surface of a wafer of semiconductor material. The process precisely specifies the degenerate (or...
4216029 Method of making static induction transistor logic  
A method of fabricating a static induction transistor device comprising providing a semiconductor substrate having a high impurity concentration, and forming a low impurity concentration...
4216030 Process for the production of a semiconductor component with at least two zones which form a pn-junction and possess differing conductivity types  
A semiconductor component is described which includes two zones of opposite conductivity type having a pn junction therebetween, and in which one zone is formed of a monocrystalline semiconductor...
4210466 Process for preparing heat sensitive semiconductor switch  
A process for preparing heat sensitive semiconductor switch which switches from OFF state to ON state at relatively low temperature. In a heat sensitive thyristor having PNPN four layer structure,...
4197630 Method of fabricating MNOS transistors having implanted channels  
The method of forming an MNOS transistor having a stepped channel oxide region utilizes intentional undercutting of the oxide in the channel region to provide a self-aligned mask for ion implanting...
4196507 Method of fabricating MNOS transistors having implanted channels  
The method of forming an MNOS transistor having a stepped channel oxide region utilizes intentional undercutting of the oxide in the channel region to provide a self-aligned mask for ion implanting...
4196228 Fabrication of high resistivity semiconductor resistors by ion implanatation  
This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder...
4187124 Process for doping semiconductors  
A process and apparatus for doping a substrate by ion implantation or discharge. The process comprises the steps of maintaining an electric discharge in an evacuated enclosure containing a gaseous...
4178191 Process of making a planar MOS silicon-on-insulating substrate device  
An improved process of forming planar silicon-on-sapphire MOS integrated circuit devices by a local oxidation process in which portions of a silicon layer on a sapphire substrate are thermally...
4169740 Method of doping a body of amorphous semiconductor material by ion implantation  
To provide for effective doping and obtain substantial conductivity change in amorphous semiconductor material, typically silicon, a body of said material is raised to a temperature above about...
4168990 Hot implantation at 1100°-1300° C. for forming non-gaussian impurity profile  
A process is described for the particular control of process variables to produce any predetermined impurity concentration within a semiconductor body according to the relation ##EQU1## WHERE...
4168997 Method for making integrated circuit transistors with isolation and substrate connected collectors utilizing simultaneous outdiffusion to convert an epitaxial layer  
In an integrated circuit structure a subsurface isolation layer is doped by diffusion during wafer processing. A substrate is first doped by ion implantation to create surface layer of the opposite...
4167425 Method for producing lateral bipolar transistor by ion-implantation and controlled temperature treatment  
A lateral bipolar transistor has a semiconductor substrate of first conductivity type with an epitaxial layer arranged thereon of second conductivity type. Collector and emitter zones of first...
4155778 Forming semiconductor devices having ion implanted and diffused regions  
A method for making ion implanted resistors in conjunction with transistors and other devices within an integrated circuit semiconductor substrate. The implantation of the resistors is done after a...
4155777 Zener diode incorporating an ion implanted layer establishing the breakdown point below the surface  
A zener diode in which the anode region of a first conductivity material is formed by diffusion in a semiconductor body, a cathode region of a second conductivity material is formed by diffusion in...
4151009 Fabrication of high speed transistors by compensation implant near collector-base junction  
A high speed bipolar transistor is obtained by the use of ion implanted compensating impurities into the base region near the collector-base junction. This compensating implant significantly...
4151008 Method involving pulsed light processing of semiconductor devices  
A pulsed laser or flash lamp produces a short duration pulse of light for thermal processing of selected regions of a semiconductor device. The light pulse is directed towards the semiconductor...
4151540 High beta, high frequency transistor structure  
High beta, high frequency transistors require very narrow and high resistance base structures, thereby placing a low limit of collector-emitter voltages that may be used without encountering...
4144098 P.sup.+ Buried layer for I.sup.2 L isolation by ion implantation  
A selected transistor in an integrated circuit formed in an N-type substrate is isolated from the substrate and from other transistors formed therein by surrounding an N-type island within the...
4144100 Method of low dose phoshorus implantation for oxide passivated diodes in <10> P-type silicon  
Low dosage phosphorus implantation regions in <100> P-type silicon are subjected to a severe damage implant with halogen or silicon ions, preferably fluorine and chlorine. This permits anneal...
4137457 Method of producing implanted areas in a substrate  
Implanted areas are produced on a substrate by irradiating the surface of the substrate with two coherent high kinetic energy beams which are superimposed in relation to one another and spaced from...
4137103 Silicon integrated circuit region containing implanted arsenic and germanium  
A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 × 10...
Matches 401 - 450 out of 497 < 1 2 3 4 5 6 7 8 9 10 >