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5290711 Method for fabricating semiconductor devices which lessens the effect of electrostatic discharge  
In a method for fabricating a semiconductor device of the present invention, photoresist layers are not formed on a scribe line regions entirely. Therefore, electric charge can be transferred from...
5254484 Method for recrystallization of preamorphized semiconductor surfaces zones  
A method for thermal annealing of amorphous surface layers on a single-crystal semiconductor base element. The amorphous surface layer is obtained by implantation of germanium or silicon ions in a...
5244820 Semiconductor integrated circuit device, method for producing the same, and ion implanter for use in the method  
The present invention relates to an ion implantation process in a wafer process for a semiconductor integrated circuit device. Particularly, according to the present invention, a shallow junction...
5238858 Ion implantation method  
An ion implantation method for forming a high concentration dopant implanted layer in a semiconductor substrate comprising irradiating an ion beam of a desired dopant in the semiconductor substrate...
5236865 Method for simultaneously forming silicide and effecting dopant activation on a semiconductor wafer  
A method for forming silicides while simultaneously activating underlying silicon substrate active regions eliminates the need for separate annealing of the active region following ion-implantation...
5223445 Large angle ion implantation method  
An ion implanting method which suppresses defects by changing the shape of the amorphous layer formed by ion injection from that of a conventional device. After forming a mask pattern on a...
5219798 Method of heating a semiconductor substrate capable of preventing defects in crystal from occurring  
In a method of heating a semiconductor substrate according to the present invention, a predetermined atmospheric gas such as N 2 , O 2 and H 2 , is sprayed onto the surface of an impurity layer...
5145794 Formation of shallow junction by implantation of dopant into partially crystalline disordered region  
A process for producing a semiconductor device, in which a predetermined electroconductive type ion is implanted into a semiconductor substrate, the process comprising the steps of: prior to the...
5130261 Method of rendering the impurity concentration of a semiconductor wafer uniform  
According to this invention, there is provided to a method of manufacturing semiconductor devices including the steps of ion-implanting at least one impurity selected from As, P, Sb, Si, B, Ga, and...
5098852 Method of manufacturing a semiconductor device by mega-electron volt ion implantation  
A method of manufacturing a semiconductor device includes forming desired semiconductor elements in a major surface region of a semiconductor substrate, and ion-implanting a selected element into...
5075242 Method of manufacturing CMOS semiconductor device having decreased diffusion layer capacitance  
A method of manufacturing a CMOS semiconductor device includes the step of preparing a substrate having a first region of a second conductivity type serving as prospective source and drain...
5024954 Method of improving high temperature stability of PTSI/SI structure  
A method of improving the high temperature stability of PtSi/Si structure is disclosed. A sufficient amount of fluorine-contained ion is implanted into the PtSi/Si structure or Pt/Si structure or...
5024723 Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning  
A method for forming a thin crystal layer of silicon on top of a insulating layer that is supported by a silicon wafer used for electronic device applications. Carbon ions are implanted in a...
5015593 Method of manufacturing semiconductor device  
In order to eliminate unwanted crystal defects generated by an ion implantation, a semiconductor substrate or an epitaxial layer, which is selectively subjected to an impurity ion implantation, is...
5011784 Method of making a complementary BiCMOS process with isolated vertical PNP transistors  
A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps...
4968637 Method of manufacture TiW alignment mark and implant mask  
A method for defining simultaneously contact implants for source and drain regions and alignment markers for a gate electrode on a channel region includes the steps of providing a refractory metal...
4889819 Method for fabricating shallow junctions by preamorphizing with dopant of same conductivity as substrate  
Shallow junctions of a first conductivity type in a semiconductor of the opposite conductivity type are fabricated by doping the substrate with a dopant of an opposite conductivity type than the...
4851691 Method for photoresist pretreatment prior to charged particle beam processing  
A method for pretreatment of a photoresist layer adhered to a semiconductor wafer prior to charged particle beam processing. The method includes bombarding the photoresist layer with ions which are...
4806497 Method for producing large-area power semiconductor components  
A method for producing large-area power semiconductor components, wherein at least two irradiation processes (neutron irridiation, ion implantation electron, γor proton irradiation) are used to...
4801555 Double-implant process for forming graded source/drain regions  
A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high...
4771011 Ion-implanted process for forming IC wafer with buried-Zener diode and IC structure made with such process  
A new process making it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse...
4762802 Method for preventing latchup in CMOS devices  
The present invention relates to a CMOS structure, and method for forming the same, which prevents latchup in MOS devices. The method is directed to the CMOS structure and functions to reduce the...
4742015 Method for producing a protective arrangement for a field-effect transistor  
The invention relates to a protective arrangement for field-effect transistors with an insulated gate electrode. An integrated, indiffused protective diode whose breakdown voltage is smaller than...
4732866 Method for producing low noise, high grade constant semiconductor junctions  
Zener diodes and other semiconductor junctions having very low noise characteristics and improved yield may be obtained by first ion implanting a suitable impurity into a substrate wafer, and then...
4729964 Method of forming twin doped regions of the same depth by high energy implant  
First conductivity type impurity ions are implanted at a predetermined depth all over a region where impurity ions are to be implanted, and second conductivity type impurity ions are implanted in a...
4725810 Method of making an implanted resistor, and resistor obtained thereby  
This method of making an implanted resistor comprises the steps of implanting the resistor with ordinary techniques and deposition over the implanted resistor of a polysilicon layer having a set...
4676845 Passivated deep p/n junction  
A passivated deep p/n junction obtained by ion implantation is disclosed. The passivated deep p/n junction is formed in a wafer, preferably a silicon wafer, thus providing an emitter region that is...
4663830 Forming deep buried grids of implanted zones being vertically and laterally offset by mask MEV implant  
A buried grid structure is produced in a semiconductor material particularly a silicon wafer, while using a metallic grid mask. The buried grid is formed directly within the semiconductor material...
4662061 Method for fabricating a CMOS well structure  
A process is disclosed for fabricating N-wells in a P-type substrate. An N-type epitaxial layer is formed on the surface of a P+ substrate. The N-type epitaxial layer is then masked and a doubly...
4649626 Semiconductor on insulator edge doping process using an expanded mask  
Edge conduction in a silicon-on-sapphire transistor is minimized by a process which permits precise doping of the edge channel regions of the transistor. The silicon island (19) containing the...
4642881 Method of manufacturing nonvolatile semiconductor memory device by forming additional impurity doped region under the floating gate  
A method of manufacturing a nonvolatile semiconductor memory device having a gate oxide layer including a relatively thin silicon dioxide layer. This gate oxide layer including the thin silicon...
4633289 Latch-up immune, multiple retrograde well high density CMOS FET  
A high density CMOS device structure that is essentially immune to latch-up, and a method of fabricating the structure, is described. This is obtained by providing a well region within and adjacent...
4617066 Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing  
A method for producing hyperabrupt P± or N± regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a...
4584026 Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions  
A process of forming a low-dose ion implant of one or more of phosphorus, arsenic or boron is described. The desired impurity ion implant is preceded by an amorphizing implant of at least about 10...
4577396 Method of forming electrical contact to a semiconductor substrate via a metallic silicide or silicon alloy layer formed in the substrate  
A silicide layer or silicon alloy layer is formed within a surface region of an impurity-doped region on the surface of a semiconductor substrate by implanting and heating any of those metals which...
4559696 Ion implantation to increase emitter energy gap in bipolar transistors  
The suppression of the reverse injection of the carriers in a bipolar transistor, without adversely effecting forward injection, is carried out by modifying the energy gap characteristics of the...
4553315 N Contact compensation technique  
The contact for N channel devices in a CMOS process is formed by ion implanting N-type impurities through contact apertures in the dielectric layer to a depth less than the source and drain regions...
4546534 Semiconductor device manufacture  
A first masking layer on a semiconductor body is defined by exposing a layer of negative acting radiation sensitive resist to a radiation pattern through a mask. Doped regions are then formed at...
4535532 Integrated circuit contact technique  
Source-drain to substrate shorts and allied problems related to misalignment of contact windows are curable in CMOS technology by a non-selective implant into the contact windows of both types. Key...
4532700 Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer  
A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a...
4522657 Low temperature process for annealing shallow implanted N+/P junctions  
Disclosed is a low temperature technique for annealing implantation damage and activating dopants. Conventional furnace annealing requires temperatures as high as 1000° to 1100° C. to completely...
4521256 Method of making integrated devices having long and short minority carrier lifetimes  
A process for producing a semiconductor device by which the minority carrier lifetime can be selectively changed in a semiconductor device. A radiation beam is irradiated onto the surface of a...
4512816 High-density IC isolation technique capacitors  
A semiconductor substrate having an epitaxial layer on its upper surface is provided with a masking layer. Holes are photolithographically etched in the masking layer where isolation diffusion...
4498224 Method of manufacturing a MOSFET using accelerated ions to form an amorphous region  
A method for manufacturing MOSFET type semiconductor devices comprises forming a gate insulation layer and a gate electrode on a single crystal semiconductor substrate; introducing impurities in...
4482393 Method of activating implanted ions by incoherent light beam  
A process of manufacturing a semiconductor device having the steps of implanting impurity ions to a surface of a semiconductor substrate; and radiating the substrate with incoherent light of which...
4472874 Method of forming planar isolation regions having field inversion regions  
A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation material comprising the following steps of: (a) providing a mask pattern on a...
4462150 Method of forming energy beam activated conductive regions between circuit elements  
A method of manufacturing semiconductor devices is disclosed. In the method, a redundancy circuit is formed by forming circuit elements making up an integrated circuit on a semiconductor substrate...
4456489 Method of forming a shallow and high conductivity boron doped layer in silicon  
Implanting, with low energy (e.g. 75 Kev and below), a dose of boron difluoride (BF 2 ) into an area on a silicon substrate which is post-damaged or pre-damaged by a silicon implant so that...
4445270 Low resistance contact for high density integrated circuit  
A novel process for fabricating low resistance contacts for high density integrated circuits is described wherein during the initial processing of the device, after a scaled MOSFET is formed,...
4441932 Process for preparing semiconductor device having active base region implanted therein using walled emitter opening and the edge of dielectric isolation zone  
A process for preparing a semiconductor device having a walled emitter structure covering at least one side surface with a dielectric layer for separation of devices comprises a step of forming a...
Matches 351 - 400 out of 497 < 1 2 3 4 5 6 7 8 9 10 >