Matches 201 - 250 out of 497 < 1 2 3 4 5 6 7 8 9 10 >
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6451674 Method for introducing impurity into a semiconductor substrate without negative charge buildup phenomenon  
A method for introducing an impurity includes the steps of: introducing an impurity having charges into a target to be processed, such as a semiconductor substrate and a film formed on a substrate;...
6429054 Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions  
A method of forming a semiconductor-on-insulator (SOI) device. The method includes providing an SOI wafer having an active layer, a substrate and a buried insulator layer therebetween; defining an...
6426535 Semiconductor device having improved short channel resistance  
First, first conductivity type impurities are injected into a semiconductor substrate to selectively form a first conductivity type region. Next, second conductivity type impurities higher in...
6423605 Method and apparatus for forming ultra-shallow junction for semiconductor device  
A practical, low-cost method for forming an ultra-shallow junction in a semiconductor material is provided. The method is directed to an initial RTA process using a heat source at a selected...
6423602 Circuit manufacturing method and apparatus, anneal control method and apparatus, information storage medium  
A silicon substrate including an impurity doped thereinto is raised in temperature to a predetermined annealing temperature, and then the temperature of the silicon substrate reaching the annealing...
6423601 Retrograde well structure formation by nitrogen implantation  
Submicron-dimensioned, p-channel MOS transistors and CMOS devices a formed using nitrogen and boron co-implants for forming p-type well regions, each implant having a parabolically-shaped...
6410409 Implanted barrier layer for retarding upward diffusion of substrate dopant  
Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron...
6410430 Enhanced ultra-shallow junctions in CMOS using high temperature silicide process  
A process of fabricating a CMOS device having an enhanced ultra-shallow junction in which substantially no transient enhanced diffusion of dopant occurs is provided. Specifically, the CMOS device...
6399452 Method of fabricating transistors with low thermal budget  
A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by...
6391746 Gettering regions and methods of forming gettering regions within a semiconductor wafer  
In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a...
6380044 High-speed semiconductor transistor and selective absorption process forming same  
A high-speed semiconductor transistor and process for forming same. The process includes forming, in a Si substrate ( 10 ), spaced apart shallow trench isolations (STIs) ( 20 ), and a gate ( 36 )...
6376276 Method of preparing diamond semiconductor  
There is provided a method of reliably preparing a diamond semiconductor by irradiating diamond with a corpuscular ray. In this method, when a diamond substrate is irradiated with a corpuscular...
6376343 Reduction of metal silicide/silicon interface roughness by dopant implantation processing  
Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or...
6376321 Method of making a pn-junction in a semiconductor element  
A pn-junction in a semiconductor element is made in that, within a zone of a first conductivity type, by means of implantation, a first and second zone of a second conductivity type are formed...
6372566 Method of forming a silicide layer using metallic impurities and pre-amorphization  
An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of:...
6372582 Indium retrograde channel doping for improved gate oxide reliability  
Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for “latch up” are formed by removing residual indium dopant utilized for forming a retrograde-shaped...
6372591 Fabrication method of semiconductor device using ion implantation  
A fabrication method of a semiconductor device is provided, which makes it possible to form shallow extensions (e.g., 0.1 μm or less in depth) of source/drain regions of a MOSFET with a double...
6368928 Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects  
A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region,...
6369434 Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors  
A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to...
6368926 Method of forming a semiconductor device with source/drain regions having a deep vertical junction  
The present invention is directed to a method of forming source/drain regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a...
6362075 Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide  
Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle...
6361874 Dual amorphization process optimized to reduce gate line over-melt  
A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep...
6362063 Formation of low thermal budget shallow abrupt junctions for semiconductor devices  
A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the...
6362081 Method to improve resistance uniformity and repeatability for low energy ion implantation  
A method of improving the resistance (Rs) uniformity and repeatability of a wafer having a silicon layer thereon is provided. The silicon layer is treated with a low energy ion implantation...
6358823 Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom  
A method of fabricating ion implanted doping layers in semiconductor materials by subjecting the material to an ultrasonic treatment during the implantation of predetermined impurities. In an...
6358803 Method of fabricating a deep source/drain  
Methods of fabricating source/drain regions and transistors incorporating the same are provided. In one aspect, a method of fabricating a source/drain region in a substrate is provided that...
6355543 Laser annealing for forming shallow source/drain extension for MOS transistor  
A method for making a ULSI MOSFET chip includes forming a transistor gate on a substrate and defining the contours of shallow source/drain extensions by implanting a first pre-amorphization (PAI)...
6346463 Method for forming a semiconductor device with a tailored well profile  
A method for forming a semiconductor device is provided. A base layer is provided. A first epitaxial layer having a first dopant at a first concentration is formed above the base layer. A second...
6346460 Low cost silicon substrate with impurity gettering and latch up protection and method of manufacture  
A low cost method of manufacturing a silicon substrate having both impurity gettering and protection against CMOS latch up. The method includes performing a low energy implant of a selected...
6346449 Non-distort spacer profile during subsequent processing  
A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source...
6342440 Method for forming low-leakage impurity regions by sequence of high-and low-temperature treatments  
A method of manufacturing a semiconductor device capable of suppressing increase of a leakage current resulting from a high-temperature heat treatment is obtained. In this manufacturing method, an...
6342413 Method of manufacturing semiconductor device  
In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask ( 311 ), wells ( 313, 314 ) and first threshold adjustment regions ( 315, 316 )...
6342438 Method of manufacturing a dual doped CMOS gate  
A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an...
6337260 Use of knocked-on oxygen atoms for reduction of transient enhanced diffusion  
Transient enhanced diffusion (TED) of ion implanted dopant impurities within a silicon semiconductor substrate is eliminated or substantially reduced by displacing “knocked-on” oxygen atoms...
6335253 Method to form MOS transistors with shallow junctions using laser annealing  
A new method of forming MOS transistors with shallow source and drain extensions and self-aligned silicide in the has been achieved. Gates are provided overlying a semiconductor substrate....
6333217 Method of forming MOSFET with channel, extension and pocket implants  
A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in...
6326219 Methods for determining wavelength and pulse length of radiant energy used for annealing  
The invention is directed to methods for determining the wavelength, pulse length and other important characteristics of radiant energy used to anneal or to activate the source and drain regions of...
6323520 Method for forming channel-region doping profile for semiconductor device  
A method for forming a semiconductor device with a doped channel-region, and the device formed therefrom. In one embodiment, the method invention is comprised of two principal steps. The first step...
6323077 Inverse source/drain process using disposable sidewall spacer  
The present invention discloses an inverse source/drain process using disposable sidewall, for forming an LDD MOSFET device on a semiconductor substrate, comprises the following steps: forming a...
6319734 Method for establishing differential injection conditions in mosfet source/drain regions based on determining the permitted amount of energy contamination with respect to desired junction depth  
A method for establishing conditions of making an index representing characteristics of a MOSFET in a permitted range by means of differentially injecting ions into a wafer. The method includes the...
6316322 Method for fabricating semiconductor device  
Submicron-dimensioned devices are formed whereby a desired relationship between the impurity concentration peak and a lightly doped source/drain region is obtained.
6300680 Semiconductor substrate and manufacturing method thereof  
A semiconductor substrate is provided which maintains its gettering capabilities throughout the manufacturing process of a semiconductor device and which prevents previously gettered contaminating...
6297111 Self-aligned channel transistor and method for making same  
A method for forming a transistor comprises the steps of: forming a gate stack on the surface of a semiconductor substrate; implanting a first dose of an impurity into the substrate at a sufficient...
6297135 Method for forming silicide regions on an integrated device  
The invented method can be used to form silicide contacts to an integrated MISFET device. Field isolation layers are formed to electrically isolate a portion of the silicon substrate, and gate,...
6297120 Method of manufacturing a semiconductor device  
To provide a method of manufacturing a semiconductor device in which an epitaxial growth film is formed on a semiconductor substrate having a buried layer, which is capable of reducing the...
6297115 Cmos processs with low thermal budget  
A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual-amorphization technique. The technique creates a shallow amorphous region and a deep...
6294433 Gate re-masking for deeper source/drain co-implantation processes  
The present invention is directed to a method of forming source/drain regions in a semiconductor device and a novel device structure. In one illustrative embodiment, the method involves forming a...
6291302 Selective laser anneal process using highly reflective aluminum mask  
A method of providing a field effect transistor includes depositing a layer of a laser-reflective material on a substrate which has an active region and an inactive region; selectively removing...
6287925 Formation of highly conductive junctions by rapid thermal anneal and laser thermal process  
For forming a highly conductive junction in an active device area of a semiconductor substrate, a first dopant is implanted into the active device area to form a preamorphization region. A second...
6284579 Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications  
A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within...
Matches 201 - 250 out of 497 < 1 2 3 4 5 6 7 8 9 10 >