Matches 1 - 50 out of 1179 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7435674 Dielectric interconnect structures and methods for forming the same  
Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g.,...
7432200 Filling narrow and high aspect ratio openings using electroless deposition  
Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the...
7427561 Method for manufacturing semiconductor device  
A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an...
7422982 Method and apparatus for electroprocessing a substrate with edge profile control  
A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a...
7419906 Method for manufacturing a through conductor  
A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first...
7416987 Semiconductor device and method of fabricating the same  
According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a...
7416942 Method for manufacturing semiconductor device  
A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate...
7413989 Method of manufacturing semiconductor device  
A semiconductor wafer including an underlying layer including an insulating film having at least one recess therein and a metallic material layer formed over a top surface of the underlying layer...
7410854 Method of making FUSI gate and resulting structure  
Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first...
7408215 Dynamic random access memory  
A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active...
7397075 Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors  
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain...
7397074 RF field heated diodes for providing thermally assisted switching to magnetic memory elements  
An exemplary array of thermally-assisted magnetic memory structures includes a plurality of magnetic memory elements, each magnetic memory element being near a diode. A diode near a selected...
7390744 Method and composition for polishing a substrate  
Polishing compositions and methods for removing conductive materials and barrier materials from a substrate surface are provided. Polishing compositions are provided for removing at least a barrier...
7384841 DRAM device and method of manufacturing the same  
In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on...
7384834 Semiconductor device and a method of manufacturing the same  
A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of...
7384833 Stress liner for integrated circuits  
In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the...
7368388 Cerium oxide abrasives for chemical mechanical polishing  
The use of mixed cerium-containing synthetic solid abrasive materials in chemical mechanical polishing slurries can provide better selectivity, better substrate removal rates, or lower defect rates...
7368383 Hillock reduction in copper films  
A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing)...
7367870 Polishing fluid and polishing method  
A polishing slurry including an oxidant, a metal oxide dissolver, a metal inhibitor and water and having a pH from 2 to 5. The metal oxide dissolver contains one or more compounds selected from one...
7367008 Adjustment of masks for integrated circuit fabrication  
A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication...
7365009 Structure of metal interconnect and fabrication method thereof  
A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first...
7363598 Dummy fill for integrated circuits  
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical...
7361603 Passivative chemical mechanical polishing composition for copper film planarization  
A CMP composition containing 5-aminotetrazole, e.g., in combination with oxidizing agent, chelating agent, abrasive and solvent and a method of use. Such CMP composition may be diluted during the...
7361598 Method for fabricating semiconductor device capable of preventing scratch  
Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell...
7361584 Detection of residual liner materials after polishing in damascene process  
A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the...
7361582 Method of forming a damascene structure with integrated planar dielectric layers  
Methods are provided for forming a circuit component on a workpiece substrate. The methods comprise the steps of depositing a dielectric material over the substrate; etching a pattern through the...
7361539 Dual stress liner  
A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate...
7356783 Dummy fill for integrated circuits  
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical...
7354530 Chemical mechanical polishing systems and methods for their use  
Alpha-amino acid containing chemical mechanical polishing compositions and slurries that are useful for polishing substrates including multiple layers of metals, or metals and dielectrics.
7354471 Coated silver-containing particles, method and apparatus of manufacture, and silver-containing devices made therefrom  
Provided are silver-containing powders and a method and apparatus for manufacturing the silver-containing particles of high quality, of a small size and narrow size distribution. An aerosol is...
7353475 Electronic design for integrated circuits based on process related variations  
A pattern-dependent model is used to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a...
7348276 Fabrication process of semiconductor device and polishing method  
A method of fabricating a semiconductor device includes a polishing process of a substrate, wherein the polishing process includes the steps of applying a chemical mechanical polishing process to...
7348231 Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses  
Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate...
7344989 CMP wafer contamination reduced by insitu clean  
Reducing CMP wafer contamination by in-situ clean is disclosed herein. The invention can be employed in a method in which a conductive layer is formed on a surface of a semiconductor wafer. After a...
7344987 Method for CMP with variable down-force adjustment  
The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed. At least one of the down-force steps...
7344954 Method of manufacturing a capacitor deep trench and of etching a deep trench opening  
A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a...
7341948 Method of making a semiconductor structure with a plating enhancement layer  
Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating...
7341908 Semiconductor device and method of manufacturing the same  
Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern...
7341649 Apparatus for electroprocessing a workpiece surface  
The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the...
7339226 Dual-level stacked flash memory cell with a MOSFET storage transistor  
The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores...
7338905 Semiconductor device manufacture method  
An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench....
7338882 Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same  
A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same...
7335239 Chemical mechanical planarization pad  
A Chemical Mechanical Planarization (CMP) Pad. The CMP pad may be hydrophobic due to the incorporation of metal complexing agents. The CMP pad substantially retaining planarazation characteristics...
7332425 Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects  
The present invention provides a method of forming a interconnect barrier layer 100 . In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 ...
7332104 Slurry for CMP, polishing method and method of manufacturing semiconductor device  
Disclosed is a CMP slurry comprising a first colloidal particle having a primary particle diameter ranging from 5 nm to 30 nm and an average particle diameter of d1, the first colloidal particle...
7329934 Smooth metal semiconductor surface and method for making the same  
A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged...
7329606 Semiconductor device having nanowire contact structures and method for its fabrication  
A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the...
7327009 Selective nitride liner formation for shallow trench isolation  
A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a...
7325206 Electronic design for integrated circuits based process related variations  
An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension...
7323095 Integrated multi-step gap fill and all feature planarization for conductive materials  
A method and apparatus is provided for depositing and planarizing a material layer on a substrate. In one embodiment, an apparatus is provided which includes a partial enclosure, a permeable disc,...
Matches 1 - 50 out of 1179 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >