Matches 651 - 700 out of 1217 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >
Match Document Document Title
6613631 Method of forming a non-volatile semiconductor memory device with a tunnel barrier film defined by side walls  
A tunnel barrier structure includes a first semiconductor ridged portion having a grooved first top surface; an insulating layer burying the groove, the insulating layer having a first upper...
6614069 Nonvolatile semiconductor memory cell and method for fabricating the memory cell  
A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is...
6613630 Nonvolatile memory device and fabricating method thereof  
A nonvolatile memory device includes two metal layers, which act respectively as a floating gate and a control gate, and each of which has a downwardly extended portion. Thereby, a surface area per...
6611020 Memory cell structure  
A new capacitor structure of a Flash memory (Flash) cells on a supporting substrate's existing topography, including existing topography provided by adjacent word lines is provided. The gate of the...
6610577 Self-aligned polysilicon polish  
A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and...
6607990 Semiconductor device and its manufacturing method  
A semiconductor device includes a semiconductor substrate; a gate oxide film made on the semiconductor substrate; and first transistors each having a first gate formed on the gate oxide film and a...
6605840 Scalable multi-bit flash memory cell and its memory array  
The scalable multi-bit flash memory cell includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region includes two stack-gate transistors and...
6602750 Container structure for floating gate memory device and method for forming same  
A floating gate memory device comprises a first conductive floating gate layer which is horizontally oriented and a second conductive floating gate layer which is predominantly vertically oriented....
6602774 Selective salicidation process for electronic devices integrated in a semiconductor substrate  
A selective silicidation process for electronic devices that are integrated on a semiconductor substrate is presented. The devices have a number of active elements formed with gate region that has...
6600188 EEPROM with a neutralized doping at tunnel window edge  
An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. P-type lightly-doped drain regions are located...
6596587 Shallow junction EEPROM device and process for fabricating the device  
A shallow junction EEPROM device and process for fabricating the device includes the formation of a control-gate region and a tunnel region in a semiconductor substrate in which the control-gate...
6596574 Method for forming a flash reference cell  
A method is used to form a flash reference memory cell and comprises the following steps. A floating well is formed in a substrate. A first dielectric layer is formed to cover the substrate. A...
6596588 Method of fabricating a flash memory cell  
A semiconductor substrate has a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape...
6597036 Multi-value single electron memory using double-quantum dot and driving method thereof  
A multi-value single electron memory using a multi-quantum dot, in which the floating gates (FG) of a EEPROM or a flash memory are formed to act as two quantum dots, and the two quantum dots are...
6594193 Charge pump for negative differential resistance transistor  
An integrated circuit device includes a charge pump for providing a bias signal to a field effect transistor (FET) that is capable of operating in a negative differential resistance mode. The bias...
6594182 Semiconductor memory device having controlled impurity concentration profile, method for manufacturing thereof, and semiconductor manufacturing apparatus  
A tunnel gate insulating film is formed on a substrate. Next, a floating gate electrode containing no impurities in the vicinities of upper and lower end surfaces is formed on the tunnel gate...
6593186 Method for manufacturing non-volatile semiconductor memory device  
In a non-volatile semiconductor memory device that has a floating gate that is formed on a semiconductor substrate with an intervening first gate insulation film, a second gate insulation film that...
6593187 Method to fabricate a square poly spacer in flash  
A square poly-spacer and making of the same are disclosed. The square poly-spacer is formed adjacent a floating poly-gate sharing a common source line with another floating poly-gate. The common...
6590260 Memory device having improved programmability  
A method for enhancing the operating characteristics of memory devices ( 400 C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate ( 406 ) and the floating gate...
6589835 Method of manufacturing flash memory  
A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition...
6589842 Manufacturing method of a gate-split flash memory  
The present invention relates to discloses a manufacturing method of a gate-split flash memory, which is suitable for a self-align contact process and fully-salicide-compatible process. The present...
6586331 Low sheet resistance of titanium salicide process  
A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSi x process by means of an additional vacuum bake. The present invention teaches an...
6587396 Structure of horizontal surrounding gate flash memory cell  
The present invention discloses a structure of a horizontal surrounding gate (HSG) flash memory cell. The HSG flash memory cell of the present invention is located on a trench of an isolation...
6586302 Method of using trenching techniques to make a transistor with a floating gate  
A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is...
6586806 Method and structure for a single-sided non-self-aligned transistor  
A transistor includes a non-self-aligned gate-terminal junction in a substrate having a relatively thick oxide layer disposed between a gate region and a terminal region and a relatively thin oxide...
6583479 Sidewall NROM and method of manufacture thereof for non-volatile memory cells  
An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a...
6583466 Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions  
A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source...
6582998 Method for fabricating nonvolatile semiconductor memory device  
Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region...
6580118 Non-volatile semiconductor memory cell having a metal oxide dielectric, and method for fabricating the memory cell  
A non-volatile semiconductor memory cell and an associated method are disclosed, in which a conventional dielectric ONO layer ( 10 ) is replaced by a very thin metal oxide layer ( 6 ) of WO x ...
6580120 Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure  
A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of...
6576515 Method of forming transistor gate  
A method of forming a transistor gate. A substrate having a source/drain terminals, a gate dielectric layer, a lower section of a floating gate, a dielectric layer over the substrate is provided....
6574143 Memory device using hot charge carrier converters  
A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling...
6573555 Source side injection programming and tip erasing P-channel split gate flash memory cell  
A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and...
6573141 In-situ etch and pre-clean for high quality thin oxides  
The present invention provides a method for improving the quality of thin oxides formed upon a semiconductor body. The etch and pre-clean processes are performed in situ, taking place in a single...
6573140 Process for making a dual bit memory device with isolated polysilicon floating gates  
The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ...
6570215 Nonvolatile memories with floating gate spacers, and methods of fabrication  
In a nonvolatile memory, a floating gate includes a portion of a conductive layer ( 150 ), and also includes conductive spacers ( 610 ). The spacers increase the capacitive coupling between the...
6570212 Complementary avalanche injection EEPROM cell  
A non-volatile memory cell at least partially formed in a semiconductor substrate, comprising a first avalanche injection element having a first active region of a first conductivity type and a...
6570211 2Bit/cell architecture for floating gate flash memory product and associated method  
The invention relates to a flash memory devices and a method associated therewith in which combined source/drain regions are shared by more than two memory cells. For example, source/drain regions...
6570209 Merged self-aligned source and ONO capacitor for split gate non-volatile memory  
A non-volatile memory cell having a oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap diffusion region is obtained by forming a film stack on a surface of a substrate, said film...
6563154 Polysilicon layer having improved roughness after POCl3 doping  
An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition...
6562682 Method for forming gate  
The invention provides a method for forming a semiconductor gate, by forming spacers to isolate the interface between the HDP dielectric layer and the polysilicon gate being exposed, thereby...
6559470 Negative differential resistance field effect transistor (NDR-FET) and circuits using the same  
An improved negative differential resistance field effect transistor (NDR-FET) is disclosed. The NDR FET includes a charge trapping layer formed at or extremely near to an interface between a...
6559007 Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide  
The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided...
6551879 Method for forming an oxide layer on a nitride layer  
A method for forming a semiconductor device that includes defining a substrate to include a peripheral section and a core section, masking the peripheral section of the substrate, growing a first...
6551946 TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE  
A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide...
6548830 Semiconductor device formed of single crystal grains in a grid pattern  
A semiconductor device comprising a source/drain region and a channel region formed in a silicon thin film composed of a group of silicon single crystal grains which are each approximately...
6548353 Method of making nonvolatile memory device having reduced capacitance between floating gate and substrate  
This invention discloses a method of making a nonvolatile memory device, wherein the capacitance between the floating gate and the substrate is reduced to result in a high capacitive coupling...
6544844 Method for forming a flash memory cell having contoured floating gate surface  
Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate, forming...
6545313 EEPROM tunnel window for program injection via P&plus contacted inversion  
An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window...
6544848 Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers  
A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric...
Matches 651 - 700 out of 1217 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >