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6680225 |
Method for manufacturing a semiconductor memory
The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for...
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6680256 |
Process for planarization of flash memory cell
A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the...
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6677198 |
Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof
The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed...
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6677204 |
Multigate semiconductor device with vertical channel current and method of fabrication
The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed....
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6677255 |
Method for removing fences without reduction of ONO film thickness
A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over...
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RE38370 |
Deposited tunneling oxide
An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein...
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6670243 |
Method of making a flash memory device with an inverted tapered floating gate
In a semiconductor memory device such as a flash memory, a field oxide film is formed to a forward taper shape on a semiconductor substrate, and a floating gate is formed to a reverse (inverted)...
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6670242 |
Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer
A method for making an integrated circuit device includes forming source and drain regions in a semiconductor substrate and defining a channel region therebetween, forming a graded, grown, gate...
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6670670 |
Single electron memory device comprising quantum dots between gate electrode and single electron storage element and method for manufacturing the same
A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory...
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6667508 |
Nonvolatile memory having a split gate
A novel structure of nonvolatile memory is formed on p type silicon and includes a stacked gate, a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One...
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6667201 |
Method for manufacturing flash memory cell
The present invention discloses a method for manufacturing a flash memory cell having a horizontal surrounding gate (HSG). The flash memory cell of the present invention is formed on a trench of an...
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6667509 |
Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash
A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory. This is accomplished in two embodiments where in the first,...
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6664601 |
Method of orperating a dual mode FET & logic circuit having negative differential resistance mode
A process for operating a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is...
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6660573 |
Method of forming a gate electrode in a semiconductor device and method of manufacturing a non-volatile memory device using the same
A method of forming a gate electrode, capable of minimizing a resistance difference between the gate electrodes and a method of forming a non-volatile memory device using the same, wherein an oxide...
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6660585 |
Stacked gate flash memory cell with reduced disturb conditions
In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron...
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6656792 |
Nanocrystal flash memory device and manufacturing method therefor
A Flash memory is provided having a trilayer structure of rapid thermal oxide/germanium (Ge) nanocrystals in silicon dioxide (SiO 2 )/sputtered SiO 2 cap with demonstrated via capacitance versus...
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6656796 |
Multiple etch method for fabricating split gate field effect transistor (FET) device
Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method...
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6656793 |
Method of forming a self-aligned floating gate in flash memory cell
A method of forming a self-aligned floating gate in a flash memory cell. A capping layer is formed on a trench insulating film. An etching process is then performed to etch the trench insulating...
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6656795 |
Method of manufacturing semiconductor memory element
A method of manufacturing a semiconductor memory element is disclosed. The method includes arranging a mask on the upper surface of a semiconductor substrate, using the mask to conduct exposure,...
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6653682 |
Non-volatile electrically alterable semiconductor memory device
Apparatus for an electrically programmable and erasable memory device and methods for programming, erasing and reading the device. The device has a single transistor including a source, a drain, a...
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6653683 |
Method and structure for an oxide layer overlying an oxidation-resistant layer
A method used during the formation of a semiconductor device such as a flash memory device includes the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a...
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6653188 |
Method of forming poly tip of floating gate in split-gate memory
The present invention provides a method for forming a floating gate with a poly tip. The method includes the step of providing a semiconductor substrate with a gate dielectric layer formed on the...
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6649473 |
Method of fabricating a floating gate for split gate flash memory
A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are...
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6649966 |
Quantum dot of single electron memory device and method for fabricating thereof
A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a...
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6649475 |
Method of forming twin-spacer gate flash device and the structure of the same
The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on...
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6649474 |
Method for fabricating a source line of a flash memory cell
A method for fabricating a source line of a flash memory cell. First, a substrate covered by a first insulating layer, a first conductive layer, and a second insulating layer successively is...
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6646301 |
Floating gate semiconductor device
A semiconductor device has a floating gate having a side wall with a generally vertical upper section and a tapered lower section and a first insulation film formed on the side wall of the floating...
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6642571 |
Nonvolatile semiconductor memory
A semiconductor memory capable of increasing the coupling ratio between a diffusion layer and a floating gate by reducing the coupling ratio between the floating gate and a control gate thereby...
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6642108 |
Fabrication processes for semiconductor non-volatile memory device
A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly...
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6642570 |
Structure of flash memory with high coupling ratio
The flash memory structure includes a substrate having trenches formed therein, a first dielectric layer and a first conductive layer are stacked on the substrate. Isolations are formed in the...
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6642563 |
Semiconductor memory including ferroelectric gate capacitor structure, and method of fabricating the same
A semiconductor memory including a ferroelectric gate capacitor structure includes an insulating interlayer formed on the surface of a semiconductor substrate. The insulating interlayer includes a...
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6642110 |
Flash memory cell and method of manufacturing the same
There is disclosed a flash memory cell and method of manufacturing the same, in which the circular hole is formed in the insulating film formed on the silicon substrate, the floating gate having a...
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6642107 |
Non-volatile memory device having self-aligned gate structure and method of manufacturing same
A method for manufacturing a non-volatile memory device including a self-aligned gate structure, and a non-volatile memory device manufactured by the same method, are provided. In the method for...
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6635922 |
Method to fabricate poly tip in split gate flash
A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the...
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6630383 |
Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer
In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming...
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6627494 |
Method for forming gate electrode of flash memory
The present invention discloses a method for forming a gate electrode of a flash memory. A tunnel oxide film is formed on the whole surface of a semiconductor substrate. A conductive film of a...
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6627962 |
Semiconductor memory
A semiconductor memory and its manufacturing method enable high-integrated memory cell to be realized easily. The semiconductor memory according to the present invention has an impurity diffusion...
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6627927 |
Dual-bit flash memory cells for forming high-density memory arrays
The dual-bit flash memory cells of the present invention include three regions: the gate region, the first-side region, and the second-side region. The gate region is formed between the first-side...
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6627501 |
Method of forming tunnel oxide layer
A method of forming a tunnel oxide layer is disclosed. The method of the present invention uses the rapid thermal process (RTP) rather than the conventional furnace process. The silicon dioxide...
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6624027 |
Ultra small thin windows in floating gate transistors defined by lost nitride spacers
A tiny tunnel oxide window with dimensions smaller than the minimum feature resolution of the process equipment is formed in an EEPROM structure by placing dummy nitride spacers on either side of a...
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6624028 |
Method of fabricating poly spacer gate structure
The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined...
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6624029 |
Method of fabricating a self-aligned non-volatile memory cell
Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer...
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6624466 |
Implant method for forming Si3N4 spacer
A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming...
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6620687 |
Method of making non-volatile memory with sharp corner
A floating gate with sharp corner is disclosed. Wherein the sharp level of the sharp corners is control by the deposition thickness of the conductive spacers. The method comprises forming a first...
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6621116 |
Enhanced EPROM structures with accentuated hot electron generation regions
An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of...
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6620684 |
Method of manufacturing nonvolatile memory cell
The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the...
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6620714 |
Method for reducing oxidation encroachment of stacked gate layer
A method for reducing oxidation encroachment of stacked gate layer is provided by forming a silicon oxynitride layer on the sidewall surface of the stacked gate layer. A tilted ion implantation...
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6620705 |
Nitriding pretreatment of ONO nitride for oxide deposition
A method of forming a dielectric structure for a flash memory cell includes forming a first layer of silicon dioxide, forming a layer of silicon nitride on the first layer of silicon dioxide, and...
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6620681 |
Semiconductor device having desired gate profile and method of making the same
In a method of manufacturing a non-volatile memory or other semiconductor device, a control gate made of conductive material is formed in a more uniform fashion. The method includes forming a...
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6617639 |
Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the...
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