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9041229 Merged fiducial for semiconductor chip packages  
Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate...
9035474 Method for manufacturing a semiconductor substrate  
The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming...
9034720 Litho scanner alignment signal improvement  
A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a...
9035308 Semiconductor package and method of fabricating the same  
A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot...
9029855 Layout for reticle and wafer scanning electron microscope registration or overlay measurements  
A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and...
9029986 Transistors with dual layer passivation  
Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor...
9030032 Semiconductor device with peeling prevention marks and shield film  
Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film...
9024457 Semiconductor device and method for manufacturing the same  
A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks...
9024456 Photolithography alignment mark, mask and semiconductor wafer containing the same mark  
A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with...
9018073 Method of manufacturing a semiconductor device including alignment mark  
A method of manufacturing a semiconductor device includes: forming a recessed portion in a semiconductor substrate; forming an insulating film in the recessed portion; after forming the insulating...
9007584 Simultaneous measurement of multiple overlay errors using diffraction based overlay  
A plurality of overlay errors in a structure is determined using a target that includes a plurality of diffraction based overlay pads. Each diffraction based overlay pad has the same number of...
9000525 Structure and method for alignment marks  
The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and...
8994197 Alignment mark and method of manufacturing the same  
An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end...
8994196 System and method for directional grinding on backside of a semiconductor wafer  
A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a...
8987922 Methods and apparatus for wafer level packaging  
A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring....
8987840 Edge-mounted sensor  
Sensor packages and methods for making a sensor device package for side mounting on a circuit board. A sensor device(s) in a mechanical layer of silicon is sandwiched between first and second...
8975763 Semiconductor memory device and method of manufacturing the same  
According to one embodiment, a semiconductor memory device includes an electrical terminal disposed in a first side; a first surface including a first part, a second part, and a third part, a mark...
8969879 Solid state image pickup device and method of producing solid state image pickup device  
Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate...
8963346 Semiconductor wafer and semiconductor device  
A semiconductor wafer may include: a disk-shaped wafer body made of silicon; and an identification trench section having at least one trench and provided at a periphery section of the wafer body,...
8963313 Heterogeneous chip integration with low loss interconnection through adaptive patterning  
Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor...
8956946 Active pad patterns for gate alignment marks  
Methods for forming RX pads having gate alignment marks configured to enable noise reduction between layers while resulting in little or no non-uniformity of CMP processes for the IC, and the...
8957504 Integrated structure with a silicon-through via  
An integrated structure with a silicon-through via includes a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and...
8956947 Method for manufacturing semiconductor substrate  
A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an...
8952454 SOI wafer and method of manufacturing the same  
An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main...
8952555 Semiconductor device and a method of manufacturing the same  
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip...
8946883 Wafer level fan-out package with a fiducial die  
A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers...
8941832 Lateral shift measurement using an optical technique  
Alignment of layers during manufacture of a multi-layer sample is controlled by applying optical measurements to a measurement site in the sample. The measurement site includes two diffractive...
8933447 Method and apparatus for programmable device testing in stacked die applications  
A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a...
8928159 Alignment marks in substrate having through-substrate via (TSV)  
A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
8922774 Method of manufacturing device, and substrate  
A method includes a first step of forming a circuit pattern and an alignment mark on a substrate and a second step of measuring a position of the alignment mark and positioning the substrate. The...
8921013 System and method for test pattern for lithography process  
A lithographic mask reticle includes a first mask region having a first mask pattern configured for use in fabrication of electronic circuit structures, and a second mask region having a second...
8912671 Semiconductor device having alignment mark  
A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment...
8900919 Robust ink formulations for durable markings on microelectronic packages and its extendibility as a barrier material for thermal and sealant materials  
Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The...
8901756 Chip positioning in multi-chip package  
Embodiments of the present invention include a substrate package, a method for multi-chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference...
8896136 Alignment mark and method of formation  
In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the...
8896137 Solid-state image pickup device and a method of manufacturing the same  
A solid-state image pickup device includes: a silicon layer; a pixel portion formed in the silicon layer for processing and outputting signal charges obtained by carrying out photoelectric...
RE45245 Apparatus and methods for determining overlay of structures having rotational or mirror symmetry  
Disclosed are overlay targets having flexible symmetry characteristics and metrology techniques for measuring the overlay error between two or more successive layers of such targets. Techniques...
8884402 Circuit layout structure  
A circuit layout structure includes a wafer having at least a cell region and a scribe line region defined thereon, a metal pattern formed in a first insulating layer in the scribe line region, a...
8853868 Semiconductor structures including sub-resolution alignment marks  
A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one...
8847416 Multi-layer chip overlay target and measurement  
A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length...
8841783 Semiconductor device and method of manufacturing semiconductor device  
A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection...
8841784 Semiconductor apparatus and substrate  
A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall...
8823936 Structure for critical dimension and overlay measurement  
The invention provides a structure for critical dimension and overlay measurement including a measuring unit, a first measurement pattern for measuring overlay and a second measurement pattern for...
8822343 Enhanced FinFET process overlay mark  
An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having...
8816707 Misalignment detection devices  
A misalignment detection device comprising a first substrate, at least one integrated circuit, a second substrate, a third substrate, and at least one detection unit. The at least one integrated...
8810048 3D IC and 3D CIS structure  
An embodiment integrated circuit includes a first device supporting a first back end of line layer, the first back end of line layer including a first alignment marker, and a second device...
8796088 Semiconductor device and method of fabricating the same  
A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the...
8785930 Method for indexing dies comprising integrated circuits  
Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage...
8786112 Leadframe, semiconductor device, and method of manufacturing the same  
A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip...
8778779 Semiconductor device and a method for producing semiconductor device  
A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and...