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6566738 |
Lead-over-chip leadframes
Lead-over-chip leadframes for coupling chip bond pads to the pins of a memory package contain a first plurality of short leads for coupling data chip bond pads to data pins on a first side of the...
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6566758 |
Current crowding reduction technique for flip chip package technology
A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can...
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6563226 |
Bonding pad
A wire bonding pad of a semiconductor integrated circuit device includes a first, test portion to which a probe tip may be contacted, and a second, wire bonding portion to which a wire is bonded...
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6563214 |
Electronic component and method of manufacturing the same
An electronic component having a substrate on which one or more grooves are formed on its opposing side faces; electrodes formed on the groove and top and bottom faces of the substrate at a portion...
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6559531 |
Face to face chips
An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer...
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6555907 |
High-frequency integrated circuit and high-frequency circuit device using the same
An RF signal input terminal having an RF signal input pad connected to a switching element and grounding pads adjacent to the RF signal input pad, and RF signal output terminals, so that the...
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6555914 |
Integrated circuit package via
A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary...
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6555917 |
Semiconductor package having stacked semiconductor chips and method of making the same
Embodiments of semiconductor packages containing a stack of at least two semiconductor chips are disclosed, along with methods of making the same. One embodiment includes a substrate, which may be...
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6555922 |
IC bonding pad combined with mark or monitor
A semiconductor device includes a bonding pad formed on a substrate and a mark region formed on the substrate right underneath the bonding pad, such that the mark region is covered by the bonding pad.
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6555913 |
Electronic component having a coil conductor with photosensitive conductive paste
A small size electronic component has a small direct current resistance value of conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a...
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6555923 |
Semiconductor chip having pads with plural junctions for different assembly methods
Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the...
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6555897 |
Assembly for attaching die to leads
A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over their respective bond pads, and an...
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6552436 |
Semiconductor device having a ball grid array and method therefor
A semiconductor device ( 50 ) includes a semiconductor die ( 52 ) having electronic circuitry that is connected to a substrate ( 54 ). The substrate ( 54 ) is used to interface the semiconductor...
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6552438 |
Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same
Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned...
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6548910 |
Integrated circuit element, printed circuit board and electronic device having input/output terminals for testing and operation
An integrated circuit chip includes a substrate having edges defining an inner area; circuit modules located on the substrate; and input/output terminals for inputting and outputting one or more...
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6548911 |
Multimedia chip package
A substrate unit has a first surface and a corresponding second surface, and a plurality of nodes and at least a die pad are formed on the first surface of the substrate unit. A plurality of...
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6541873 |
90 degree bump placement layout for an integrated circuit power grid
A 90 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer...
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6538307 |
Packaging substrate comprising staggered vias
A packaging substrate is formed with staggered vias interconnecting fan-out circuitry for improved strength and rigidity. Embodiments of the present invention include substrates wherein less than...
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6538337 |
Ball grid array package for providing constant internal voltage via a PCB substrate routing configuration
A ball grid array (BGA) package provides a constant internal voltage via an auxiliary routing configuration of a printed circuit board (PCB). The BGA package includes a substrate having an opening,...
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6538336 |
Wirebond assembly for high-speed integrated circuits
A semiconductor device assembly facilitates high-speed communication between an integrated-circuit die and external circuitry. The die is mounted on a wiring board that includes rows of bond sites...
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6534879 |
Semiconductor chip and semiconductor device having the chip
A semiconductor chip includes a main surface having a plurality of sides, a plurality of signal electrodes formed on the main surface along the sides, the signal electrodes along one of the sides...
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6534872 |
Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging
An apparatus and system comprising electrical interconnection devices (EIDs), such as printed wiring boards, semiconductor packages, and printed circuit boards, having novel via and signal trace...
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6534878 |
Optimizing the power connection between chip and circuit board for a power switch
For optimizing the power connection between semiconductor chip and conductor frame in a semiconductor switch, the bond wires that form the power path input of the power part are symmetrically...
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6531709 |
Semiconductor wafer and fabrication method of a semiconductor chip
The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present...
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6531782 |
Method of placing die to minimize die-to-die routing complexity on a substrate
A method of fabricating a semiconductor package that may contain two or more dies. The method generally comprises the steps of (A) mounting a first die having a first side on an assembly apparatus...
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6528882 |
Thermal enhanced ball grid array package
A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating...
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6528872 |
Packaging structure for ball grid array
A ball grid array packaging structure for sealing a silicon chip on a substrate is disclosed. The substrate includes a front wiring layer and a back wiring layer. The front wiring layer includes a...
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6528873 |
Ball grid assembly with solder columns
A method of making a ball grid assembly and the assembly wherein a mask ( 1 ) is provided which is not wettable by solder and through which a pattern of parallel holes ( 3 ) is provided extending...
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6521354 |
Epoxy resin composition and semiconductor device
An epoxy resin comprising (A) an epoxy resin, (B) a curing agent and (C) a filler, in which the epoxy resin (A) contains a bisphenol F-type epoxy compound (a), the filler (C) contains spherical...
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6522022 |
Mounting structure for semiconductor devices
A mounting structure for semiconductor devices wherein a plurality of semiconductor devices each comprised of a semiconductor chip carried on a substrate and provided with connection terminals...
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6518512 |
Structure for inspecting electrical component alignment
According to a structure for inspecting the alignment of a mounted electrical component of the present invention, a wiring pattern has fiducial portions extending closely along at least two outer...
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6518663 |
Constant impedance routing for high performance integrated circuit packaging
An electrical connection web, operable at high frequency and configured on a dielectric substrate, comprising a plurality of generally parallel signal lines having graduated width and variable...
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6515366 |
Reduction of metal corrosion in semiconductor devices
Reducing metal corrosion, such as copper corrosion, in semiconductor devices, is disclosed. A semiconductor device includes an insulating layer, a metal line, one or more corrosive metal...
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6515364 |
Semiconductor device
A semiconductor device having buried oxide film ( 11 ) and a diffusion layer ( 12 ) formed in an alternating pattern. A CMP method can be used to create a planar surface. Polycide ( 13 ) can be...
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6512180 |
Printed-wiring board, method for identifying same, and method for manufacturing same
A printed-wiring board to be mounted with a circuit element includes a plurality of pads which assist in an electric connection between the circuit element and a wiring pattern, at least one of...
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6509582 |
Semiconductor pad construction enabling pre-bump probing by planarizing the post-sort pad surface
A visual pattern of insulating material is used to guide visually the placement of test probes on a semiconductor wafer. A passivation layer is patterned over the probed areas on the wafer, and...
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6509638 |
Semiconductor device having a plurality of stacked semiconductor chips on a wiring board
A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected...
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6507114 |
BOC semiconductor package including a semiconductor die and a substrate bonded circuit side down to the die
A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the...
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6507099 |
Multi-chip integrated circuit carrier
An integrated circuit carrier includes a plurality of receiving zones. Each receiving zone includes electrical contacts and each receiving zone is configured to receive a particular type of...
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6507094 |
Die paddle clamping for wire bond enhancement
A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to...
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6507104 |
Semiconductor package with embedded heat-dissipating device
A semiconductor package with an embedded heat-dissipating device is proposed. The heat-dissipating device including a heat sink and a plurality of connecting bumps attached to connecting pads...
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6504252 |
Semiconductor device with a split pad electrode
A semiconductor device of the present invention comprises a first split Pad electrode which is electrically connected to wirings and a MOSFET and a second split Pad electrode which is not...
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6504239 |
Semiconductor device having dummy pattern that relieves stress
A semiconductor device includes a base substrate which has four sides, a first major surface and a second major surface opposite to the first major surface, and a semiconductor chip which is...
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6504241 |
Stackable semiconductor device and method for manufacturing the same
There is provided a semiconductor device having a semiconductor chip in which a first protrusion electrode is formed on the semiconductor substrate; and an intermediate substrate which comprises a...
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6501186 |
Bond pad having variable density via support and method for fabrication
A bond pad structure that is supported by a multiplicity of vias arranged in at least two regions each having a different via density than the other and a method for forming the structure are...
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6501164 |
Multi-chip semiconductor package with heat dissipating structure
A multi-chip semiconductor package with a heat dissipating structure is proposed, in which a chip receiving cavity and an opening respectively formed in the heat dissipating structure and a chip...
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6500764 |
Method for thinning a semiconductor substrate
A method for thinning a semiconductor substrate that does not impose a significant risk of breakage on the semiconductor substrate itself and is compatible with semiconductor wafers having...
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6498389 |
Ultra-thin semiconductor package device using a support tape
An ultra-thin semiconductor package device comprises a heat-resistant film-type adhesive support tape which connects a semiconductor chip to a plurality of individual lead frames, wherein each lead...
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6498396 |
Semiconductor chip scale package and ball grid array structures
An external interconnection unit including a pad provided on a semiconductor chip, a bump electrode formed on a main surface of a semiconductor chip for connection with the board, and a connection...
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6495925 |
Semiconductor chip and a lead frame
A semiconductor chip includes a semiconductor substrate having an electronic circuit theron and a number of bond pads thereon. The bond pads are coupled to the electronic circuit and permit power...
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