Matches 651 - 700 out of 1417 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >
Match Document Document Title
6646355 Structure comprising beam leads bonded with electrically conductive adhesive  
A new interconnection scheme is disclosed for a tape automated bonding (TAB) package, a flip chip package and an active matrix liquid crystal display (AMLCD) panel, where an electrically conducting...
6642627 Semiconductor chip having bond pads and multi-chip package  
A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is...
6638792 Method for fabricating BOC semiconductor package  
A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the...
6638793 Methodology to pack standard staggered bond input-output buffer into linear input-output buffer  
A new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad...
6630730 Semiconductor device assemblies including interposers with dams protruding therefrom  
A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the...
6630744 Multichip module  
A small multichip module has a mother chip and a stack chip. The stack chip is stacked on the mother chip. The mother chip includes a first bonding pad located in a circuit area. A bonding pad of...
6628001 Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same  
The present invention provides a die located on a semiconductor wafer. In one embodiment, the die includes a circuit region located within a circuit perimeter of the die. In addition, the die...
6627994 Semiconductor device and film carrier tape  
The present invention is a semiconductor device with improved adhesion properties of a resin with a wiring pattern, comprising a film fragment 14 having a patterned wiring pattern 16 including...
6624521 Flip chip design on a coplanar waveguide with a pseudo-coaxial ground bump configuration  
A flip chip assembly is disclosed that includes a coplanar waveguide launch with a transmission line, and a bump interconnection that includes multiple ground bumps. The transmission line may be a...
6621155 Integrated circuit device having stacked dies and impedance balanced transmission lines  
A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of...
6621154 Semiconductor apparatus having stress cushioning layer  
A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of...
6617680 Chip carrier, semiconductor package and fabricating method thereof  
A chip carrier, a semiconductor package and a fabricating method thereof are proposed, in which on one side of the chip carrier finally removed from an engaged surface of a mold in a de-molding...
6617699 120 degree bump placement layout for an integrated circuit power grid  
A 120 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer...
6617694 Semiconductor chip, semiconductor device, methods of fabricating thereof, circuit board and electronic device  
The positions of first terminals of a first semiconductor chip have a plane symmetrical relationship with the positions of second terminals of a second semiconductor chip. First buffer circuits of...
6614113 Semiconductor device and method for producing the same  
A semiconductor device includes a barrier metal structure which are sandwiched between an electrode provided on a semiconductor chip and a bump. The barrier metal structure has a first through...
6608377 Wafer level package including ground metal layer  
A semiconductor chip package includes a ground metal layer disposed in close proximity to a signal layer for carrying electrical input and output signals to and from the chip. The ground metal...
6608390 Wirebonded semiconductor package structure and method of manufacture  
A wirebonded semiconductor package structure that provides for high frequency operation, a large number of I/O terminals, controlled low impedance, compensated inductance, electromagnetic shielding...
6608382 Metal bump  
A plurality of metal bumps connecting a nonconducting substrate and a chip, consisting of: at least a first metal bump having at least one curved face, at least a second metal bump having at least...
6608379 Enhanced chip scale package for flip chips  
A chip scale package (CSP) comprises a flip chip and chip carrier with features to enhance its electrical and thermal performance. The flip chip connects to the chip carrier through alternating...
6608388 Delamination-preventing substrate and semiconductor package with the same  
A delamination-preventing substrate and a semiconductor package with the substrate are provided. A metal layer and a solder mask layer are sequentially laminated on a chip attach area of a...
6608384 Semiconductor device and method of forming the same  
A semiconductor device includes a bonding-structure for electrically and mechanically bonding a solder ball to the electrode pad. The bonding-structure includes flexible arms that are connected to...
6605875 Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size  
Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size. A lower die has keep out areas on its top surface. The keep out areas correspond...
6602778 Apparatus and methods for coupling conductive leads of semiconductor assemblies  
A method and apparatus for electrically coupling bond pads on the surface of a microelectronic device. The apparatus can include a microelectronic device having at least two bond pads with a...
6599578 Method for improving integrated circuits bonding firmness  
A method for improving the integrated circuits bonding firmness, whose principle is that after the later film is piled on top of the previous film, the upper surface of the later film will be...
6593664 Chip module with bond-wire connections with small loop height  
In a data carrier ( 1 ) with a chip module ( 3 ), the chip ( 5 ) of the chip module ( 3 ) is provided, in the region of its chip connecting layers ( 8 ), with a respective wire connecting means...
6594811 Routable high-density interfaces for integrated circuit devices  
Patterns for a routable interface of the signal lines of a integrated circuit device include several groups of terminals distributed about the pattern center, each group clustered along a...
6590296 Semiconductor device with staggered hexagonal electrodes and increased wiring width  
A semiconductor device having electrodes formed along a peripheral part thereof in a staggered arrangement of lines including inside-line electrodes, central-line electrodes and outside-line...
6590284 Semiconductor device and method of manufacturing same  
The invention relates to a semiconductor device ( 10 ) comprising an IC ( 1 ) which is attached to one side of an insulating substrate ( 11 ) which, on said side, is provided with a first conductor...
6591410 Six-to-one signal/power ratio bump and trace pattern for flip chip design  
A method for making a bump and trace layout for an integrated circuit die includes the step of replicating a routing tile having a first column of I/O pads and a second column of I/O pads wherein...
6590281 Crack-preventive semiconductor package  
A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding...
6586834 Die-up tape ball grid array package  
An integrated circuit package including a flexible circuit tape having a flexible polyimide tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to...
6586845 Semiconductor device module and a part thereof  
A semiconductor device module includes one or a plurality of semiconductor devices, each including a semiconductor element having first and second surfaces, pads formed on the first surface on...
6587008 Piezoelectric oscillator and a method for manufacturing the same  
A piezoelectric oscillator is provided with a container unit in which an upper cavity and a lower cavity are partitioned by a partition wall, a piezoelectric oscillating element accommodated in the...
6586839 Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers  
A conductive via pattern ( 110 ) between the uppermost metal interconnect layer (M n ) and next underlying metal interconnect layer (M n−1 ) in the bond pad areas strengthens the interlevel...
6586825 Dual chip in package with a wire bonded die mounted to a substrate  
A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top...
6583514 Semiconductor device with a binary alloy bonding layer  
A semiconductor device includes a semiconductor chip. A substrate is arranged in opposition to the semiconductor chip. A first electrode is placed on the semiconductor chip while a second electrode...
6583483 Semiconductor device and its manufacturing method  
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on insulated substrate 12. ...
6583444 Semiconductor packages having light-sensitive chips  
A method of making a microelectronic package includes providing a sacrificial layer having a first surface and providing an optoelectronic element having a front face including one or more contacts...
6580175 Semiconductor layout structure for a conductive layer and contact hole  
The present invention discloses a layout in a semiconductor device having conductive layers electrically connected to conductive regions via contact holes beneath the conductive layers. Each of the...
6580092 Semiconductor chip, semiconductor device, and process for producing a semiconductor device  
Obtainable are a semiconductor chip making it possible to perform a thoroughgoing test easily without imposing a burden on the circuit of its body; a semiconductor device on which the semiconductor...
6577017 Bond pad having vias usable with antifuse process technology  
A lower metal plate having a strip-like opening is used in a bond pad structure having metal plugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material...
6577008 Metal redistribution layer having solderable pads and wire bondable pads  
A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip...
6577015 Partial slot cover for encapsulation process  
A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed...
6576998 Thin semiconductor package with semiconductor chip and electronic discrete device  
Semiconductor packages including at least one semiconductor chip and at least one electronic discrete device, such as a transistor, oscillator, optical sensor, resistor, capacitor, or inductor, are...
6573592 Semiconductor die packages with standard ball grid array footprint and method for assembling the same  
Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to form a recess. An array of...
6573612 Resin-encapsulated semiconductor device including resin extending beyond edge of substrate  
A process for fabricating a resin-encapsulated semiconductor device comprises the steps of: (a) forming a plurality of first through holes for external connection in a substrate for mounting...
6570251 Under bump metalization pad and solder bump connections  
The present invention relates to an improved method of forming and structure for under bump metallurgy (“UBM”) pads for a flip chip which reduces the number of metal layers and requires the use...
6566738 Lead-over-chip leadframes  
Lead-over-chip leadframes for coupling chip bond pads to the pins of a memory package contain a first plurality of short leads for coupling data chip bond pads to data pins on a first side of the...
6566758 Current crowding reduction technique for flip chip package technology  
A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can...
6563226 Bonding pad  
A wire bonding pad of a semiconductor integrated circuit device includes a first, test portion to which a probe tip may be contacted, and a second, wire bonding portion to which a wire is bonded...
Matches 651 - 700 out of 1417 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >