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7528467 |
IC substrate with over voltage protection function
The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to...
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7521812 |
Method of wire bonding over active area of a semiconductor circuit
A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate...
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7521784 |
System for coupling wire to semiconductor region
A first device has a surface and includes a micrometer-scale or smaller geometry doped semiconductor region extending along the surface. A second device has a surface opposite the surface of the...
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7521781 |
Integrated circuit package system with mold clamp line critical area having widened conductive traces
An integrated circuit package system includes providing a substrate having a first plurality of conductive traces having a first width. An integrated circuit die is attached to the substrate. A...
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7518223 |
Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least partially spaces the surface of the...
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7518239 |
Semiconductor device with substrate having penetrating hole having a protrusion
A semiconductor device includes a substrate, a semiconductor chip, a conductive member and an external electrode. A penetrating hole is formed in the substrate, the penetrating hole having an...
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7518227 |
Multiple die stack apparatus employing T-shaped interposer elements
Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor...
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7518250 |
Semiconductor device and a method for manufacturing of the same
A first solder resist section and a second solder resist section are formed over an upper surface of a wiring board. A semiconductor chip is bonded onto the first solder resist section via an...
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7514796 |
Semiconductor chip capable of being laminated and a semiconductor device including the lamination of a plurality of semiconductor chips
To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side...
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7514790 |
Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device comprises: an insulation layer located on or above a semiconductor element; a conductive pad formed on the insulation film; and a first opening pattern formed on the...
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7514800 |
Semiconductor device and wire bonding method therefor
A semiconductor device ( 10 ) that may have a wire bonding structure having reduced interference between bond wires and a path of a capillary has been disclosed. Semiconductor device ( 10 ) may...
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7514801 |
Electronic device and method of manufacturing thereof
The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with a connection layer, an intermediate layer and contact pads. The element is present...
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7511365 |
Thermal enhanced low profile package structure
A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component...
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7507996 |
Contact structure of a wiring and a thin film transistor array panel including the same
First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is...
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7504734 |
Semiconductor device having improved solder joint and internal lead lifetimes
A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is...
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7504715 |
Packaging of a microchip device
The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically...
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7504735 |
Manufacturing method of resin-molding type semiconductor device, and wiring board therefor
A wiring board for manufacturing a resin-molding type semiconductor device includes a plurality of element regions each having a mount region on which a semiconductor element is mounted and an...
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7504728 |
Integrated circuit having bond pad with improved thermal and mechanical properties
An integrated circuit includes active circuitry and at least one bond pad. The at least one bond pad, in turn, comprises a metallization layer and a capping layer having one or more grooves. The...
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7501709 |
BGA package with wiring schemes having reduced current loop paths to improve cross talk control and characteristic impedance
A Ball Grid Array (BGA) integrated circuit package having (i) an additional dedicated ground ring on the package substrate which provides a reduced area return current loop path to reduce wire bond...
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7501337 |
Dual metal stud bumping for flip chip applications
A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a...
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7501697 |
Integrated circuit package system
An integrated circuit package system is provided forming a carrier having a top side and a bottom side, forming an edge terminal pad on the top side and an inner terminal pad on the bottom side,...
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7498680 |
Test structure
A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is...
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7498667 |
Stacked integrated circuit package-in-package system
A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first peripheral contact, forming a second integrated circuit package having a...
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7498666 |
Stacked integrated circuit
The invention relates to an integrated circuit comprising a top package with a first substrate carrying an integrated circuit, and a bottom package with a second substrate carrying at least one...
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7495327 |
Chip stacking structure
An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active...
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7494847 |
Method for making a semiconductor multi-package module having inverted wire bond carrier second package
A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and...
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7491986 |
Semiconductor integrated circuit device
A different electric power supply electric power source cell is proposed which includes paths by which electric power source voltages, the electric potentials of which are different from each...
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7489035 |
Integrated circuit chip package having a ring-shaped silicon decoupling capacitor
A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a...
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7489044 |
Semiconductor package and fabrication method thereof
The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers,...
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7489043 |
Semiconductor chip package and fabrication method thereof
A semiconductor chip package includes a first semiconductor chip, that is an MEMS chip having a movable structure. The movable structure has a movable section. The first semiconductor chip includes...
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7485908 |
Insulated gate silicon nanowire transistor and method of manufacture
An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate...
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7485973 |
Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip, a solder ball for external connection, wiring for...
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7485972 |
Semiconductor device
Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the...
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7482699 |
Semiconductor device
The present invention can supply power for each circuit section by separating and connecting bus-bar ( 21 d ) for each circuit section inside the semiconductor chip ( 22 ), and, in addition, can...
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7479705 |
Semiconductor device
A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective...
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7479702 |
Composite conductive film and semiconductor package using such film
A composite conductive film and a semiconductor package using such film are provided. The composite conductive film is formed of a polymer-matrix and a plurality of nano-sized conductive lines is...
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7476983 |
Semiconductor device including wire bonding pads and pad layout method
In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared...
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7476979 |
Chip scale surface mounted device and process of manufacture
A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose...
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7474007 |
Semiconductor package
A semiconductor package of this invention achieves higher wiring densities and increases the degree of freedom of the wiring design. The semiconductor package includes a first substrate having...
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7473943 |
Gate configuration for nanowire electronic devices
Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at...
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7470997 |
Wirebond pad for semiconductor chip or wafer
In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps...
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7470998 |
Semiconductor device and method of manufacturing the same
The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an...
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7468560 |
Semiconductor device with micro connecting elements and method for producing the same
A semiconductor device with micro connecting elements and method for producing the same disclosed. In one embodiment, the semiconductor device includes a number of micro connecting elements for the...
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7468551 |
Multiple chips bonded to packaging structure with low noise and multiple selectable functions
A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor...
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7468559 |
Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any...
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7466013 |
Semiconductor die structure featuring a triple pad organization
A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the...
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7462941 |
Power grid layout techniques on integrated circuits
Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages...
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7462887 |
Semiconductor connection component
There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit...
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7462933 |
Ball grid array package enhanced with a thermal and electrical connector
Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface...
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7459776 |
Stacked die assembly having semiconductor die projecting beyond support
A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a...
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